Scaling half-precision floating point tensors for training deep neural networks

ABSTRACT

A graphics processor is described that includes a single instruction, multiple thread (SIMT) architecture including hardware multithreading. The multiprocessor can execute parallel threads of instructions associated with a command stream, where the multiprocessor includes a set of functional units to execute at least one of the parallel threads of the instructions. The set of functional units can include a mixed precision tensor processor to perform tensor computations. The functional units can also include circuitry to analyze statistics for output values of the tensor computations, determine a target format to convert the output values, the target format determined based on the statistics for the output values and a precision associated with a second layer of the neural network, and convert the output values to the target format.

CROSS-REFERENCE

This application claims priority to U.S. application Ser. No. 16/526,376filed Jul. 30, 2019, which claims priority to U.S. application Ser. No.15/869,582 filed Jan. 12, 2018, which claims priority to Indiaprovisional patent application number 201741015600 filed on May 3, 2017,which is hereby incorporated herein by reference.

FIELD

Embodiments relate generally to data processing and more particularly tomachine learning processing via a general-purpose graphics-processingunit.

BACKGROUND OF THE DESCRIPTION

Current parallel graphics data processing includes systems and methodsdeveloped to perform specific operations on graphics data such as, forexample, linear interpolation, tessellation, rasterization, texturemapping, depth testing, etc. Traditionally, graphics processors usedfixed function computational units to process graphics data; however,more recently, portions of graphics processors have been madeprogrammable, enabling such processors to support a wider variety ofoperations for processing vertex and fragment data.

To further increase performance, graphics processors typically implementprocessing techniques such as pipelining that attempt to process, inparallel, as much graphics data as possible throughout the differentparts of the graphics pipeline. Parallel graphics processors with singleinstruction, multiple thread (SIMT) architectures are designed tomaximize the amount of parallel processing in the graphics pipeline. Inan SIMT architecture, groups of parallel threads attempt to executeprogram instructions synchronously together as often as possible toincrease processing efficiency. A general overview of software andhardware for SIMT architectures can be found in Shane Cook, CUDAProgramming, Chapter 3, pages 37-51 (2013) and/or Nicholas Wilt, CUDAHandbook, A Comprehensive Guide to GPU Programming, Sections 2.6.2 to3.1.2 (June 2013).

BRIEF DESCRIPTION OF THE DRAWINGS

So that the features of the present invention can be understood indetail, a more particular description of the invention may be had byreference to embodiments, some of which are illustrated in the appendeddrawings. It is to be noted, however, that the appended drawingsillustrate only typical embodiments and are therefore not to beconsidered limiting of the scope of all embodiments.

FIG. 1 is a block diagram illustrating a computer system configured toimplement one or more aspects of the embodiments described herein;

FIG. 2A-2D illustrate parallel processor components, according to anembodiment;

FIG. 3A-3B are block diagrams of graphics multiprocessors, according toembodiments;

FIG. 4A-4F illustrate an exemplary architecture in which a plurality ofGPUs is communicatively coupled to a plurality of multi-core processors;

FIG. 5 illustrates a graphics processing pipeline, according to anembodiment;

FIG. 6A illustrates a scaling operation to avoid information loss during16-bit training, according to an embodiment;

FIG. 6B illustrates logic to perform a scaling operation, according toan embodiment;

FIG. 7A illustrates a flow diagram of logic to perform scaled computeoperations on a layer of a deep neural network, according to anembodiment;

FIG. 7B is a flow diagram illustrating logic=to implement a dynamicscaling algorithm, according to an embodiment;

FIG. 7C is a block diagram of a data processing system, according to anembodiment;

FIG. 8 illustrates a machine learning software stack, according to anembodiment;

FIG. 9 illustrates a highly-parallel general-purpose graphics processingunit, according to an embodiment;

FIG. 10 illustrates a multi-GPU computing system, according to anembodiment;

FIG. 11A-B illustrate layers of exemplary deep neural networks;

FIG. 12 illustrates an exemplary recurrent neural network;

FIG. 13 illustrates training and deployment of a deep neural network;

FIG. 14 is a block diagram illustrating distributed learning;

FIG. 15 illustrates an exemplary inferencing system on a chip (SOC)suitable for performing inferencing using a trained model;

FIG. 16 is a block diagram of a processing system, according to anembodiment;

FIG. 17 is a block diagram of a processor according to an embodiment;

FIG. 18 is a block diagram of a graphics processor, according to anembodiment;

FIG. 19 is a block diagram of a graphics processing engine of a graphicsprocessor in accordance with some embodiments;

FIG. 20 is a block diagram of a graphics processor provided by anadditional embodiment;

FIG. 21 illustrates thread execution logic including an array ofprocessing elements employed in some embodiments;

FIG. 22 is a block diagram illustrating graphics processor instructionformats according to some embodiments;

FIG. 23 is a block diagram of a graphics processor according to anotherembodiment;

FIG. 24A-24B illustrate a graphics processor command format and commandsequence, according to some embodiments;

FIG. 25 illustrates exemplary graphics software architecture for a dataprocessing system according to some embodiments;

FIG. 26 is a block diagram illustrating an IP core development system,according to an embodiment;

FIG. 27 is a block diagram illustrating an exemplary system on a chipintegrated circuit, according to an embodiment;

FIG. 28 is a block diagram illustrating an additional exemplary graphicsprocessor; and

FIG. 29 is a block diagram illustrating an additional exemplary graphicsprocessor of a system on a chip integrated circuit, according to anembodiment.

DETAILED DESCRIPTION

In some embodiments, a graphics processing unit (GPU) is communicativelycoupled to host/processor cores to accelerate graphics operations,machine-learning operations, pattern analysis operations, and variousgeneral-purpose GPU (GPGPU) functions. The GPU may be communicativelycoupled to the host processor/cores over a bus or another interconnect(e.g., a high-speed interconnect such as PCIe or NVLink). In otherembodiments, the GPU may be integrated on the same package or chip asthe cores and communicatively coupled to the cores over an internalprocessor bus/interconnect (i.e., internal to the package or chip).Regardless of the manner in which the GPU is connected, the processorcores may allocate work to the GPU in the form of sequences ofcommands/instructions contained in a work descriptor. The GPU then usesdedicated circuitry/logic for efficiently processing thesecommands/instructions.

In the following description, numerous specific details are set forth topro a more thorough understanding. However, it will be apparent to oneof skill in the art that the embodiments described herein may bepracticed without one or more of these specific details. In otherinstances, well-known features have not been described to avoidobscuring the details of the present embodiments.

System Overview

FIG. 1 is a block diagram illustrating a computing system 100 configuredto implement one or more aspects of the embodiments described herein.The computing system 100 includes a processing subsystem 101 having oneor more processor(s) 102 and a system memory 104 communicating via aninterconnection path that may include a memory hub 105. The memory hub105 may be a separate component within a chipset component or may beintegrated within the one or more processor(s) 102. The memory hub 105couples with an I/O subsystem 111 via a communication link 106. The I/Osubsystem 111 includes an I/O hub 107 that can enable the computingsystem 100 to receive input from one or more input device(s) 108.Additionally, the I/O hub 107 can enable a display controller, which maybe included in the one or more processor(s) 102, to provide outputs toone or more display device(s) 110A. In one embodiment the one or moredisplay device(s) 110A coupled with the I/O hub 107 can include a local,internal, or embedded display device.

In one embodiment the processing subsystem 101 includes one or moreparallel processor(s) 112 coupled to memory hub 105 via a bus or othercommunication link 113. The communication link 113 may be one of anynumber of standards based communication link technologies or protocols,such as, but not limited to PCI Express, or may be a vendor specificcommunications interface or communications fabric. In one embodiment theone or more parallel processor(s) 112 form a computationally focusedparallel or vector processing system that can include a large number ofprocessing cores and/or processing clusters, such as a many integratedcore (MIC) processor. In one embodiment the one or more parallelprocessor(s) 112 form a graphics processing subsystem that can outputpixels to one of the one or more display device(s) 110A coupled via theI/O hub 107. The one or more parallel processor(s) 112 can also includea display controller and display interface (not shown) to enable adirect connection to one or more display device(s) 110B.

Within the I/O subsystem 111, a system storage unit 114 can connect tothe I/O hub 107 to provide a storage mechanism for the computing system100. An I/O switch 116 can be used to provide an interface mechanism toenable connections between the I/O hub 107 and other components, such asa network adapter 118 and/or wireless network adapter 119 that may beintegrated into the platform, and various other devices that can beadded via one or more add-in device(s) 120. The network adapter 118 canbe an Ethernet adapter or another wired network adapter. The wirelessnetwork adapter 119 can include one or more of a Wi-Fi, Bluetooth, nearfield communication (NFC), or other network device that includes one ormore wireless radios.

The computing system 100 can include other components not explicitlyshown, including USB or other port connections, optical storage drives,video capture devices, and the like, may also be connected to the I/Ohub 107. Communication paths interconnecting the various components inFIG. 1 may be implemented using any suitable protocols, such as PCI(Peripheral Component Interconnect) based protocols (e.g., PCI-Express),or any other bus or point-to-point communication interfaces and/orprotocol(s), such as the NV-Link high-speed interconnect, orinterconnect protocols known in the art.

In one embodiment, the one or more parallel processor(s) 112 incorporatecircuitry optimized for graphics and video processing, including, forexample, video output circuitry, and constitutes a graphics processingunit (GPU). In another embodiment, the one or more parallel processor(s)112 incorporate circuitry optimized for general purpose processing,while preserving the underlying computational architecture, described ingreater detail herein. In yet another embodiment, components of thecomputing system 100 may be integrated with one or more other systemelements on a single integrated circuit. For example, the one or moreparallel processor(s) 112, memory hub 105, processor(s) 102, and I/O hub107 can be integrated into a system on chip (SoC) integrated circuit.Alternatively, the components of the computing system 100 can beintegrated into a single package to form a system in package (SIP)configuration. In one embodiment at least a portion of the components ofthe computing system 100 can be integrated into a multi-chip module(MCM), which can be interconnected with other multi-chip modules into amodular computing system.

It will be appreciated that the computing system 100 shown herein isillustrative and that variations and modifications are possible. Theconnection topology, including the number and arrangement of bridges,the number of processor(s) 102, and the number of parallel processor(s)112, may be modified as desired. For instance, in some embodiments,system memory 104 is connected to the processor(s) 102 directly ratherthan through a bridge, while other devices communicate with systemmemory 104 via the memory hub 105 and the processor(s) 102. In otheralternative topologies, the parallel processor(s) 112 are connected tothe I/O hub 107 or directly to one of the one or more processor(s) 102,rather than to the memory hub 105. In other embodiments, the I/O hub 107and memory hub 105 may be integrated into a single chip. Someembodiments may include two or more sets of processor(s) 102 attachedvia multiple sockets, which can couple with two or more instances of theparallel processor(s) 112.

Some of the particular components shown herein are optional and may notbe included in all implementations of the computing system 100. Forexample, any number of add-in cards or peripherals may be supported, orsome components may be eliminated. Furthermore, some architectures mayuse different terminology for components similar to those illustrated inFIG. 1. For example, the memory hub 105 may be referred to as aNorthbridge in some architectures, while the I/O hub 107 may be referredto as a Southbridge.

FIG. 2A illustrates a parallel processor 200, according to anembodiment. The various components of the parallel processor 200 may beimplemented using one or more integrated circuit devices, such asprogrammable processors, application specific integrated circuits(ASICs), or field programmable gate arrays (FPGA). The illustratedparallel processor 200 is a variant of the one or more parallelprocessor(s) 112 shown in FIG. 1, according to an embodiment.

In one embodiment the parallel processor 200 includes a parallelprocessing unit 202. The parallel processing unit includes an I/O unit204 that enables communication with other devices, including otherinstances of the parallel processing unit 202. The I/O unit 204 may bedirectly connected to other devices. In one embodiment the I/O unit 204connects with other devices via the use of a hub or switch interface,such as memory hub 105. The connections between the memory hub 105 andthe I/O unit 204 form a communication link 113. Within the parallelprocessing unit 202, the I/O unit 204 connects with a host interface 206and a memory crossbar 216, where the host interface 206 receivescommands directed to performing processing operations and the memorycrossbar 216 receives commands directed to performing memory operations.

When the host interface 206 receives a command buffer via the I/O unit204, the host interface 206 can direct work operations to perform thosecommands to a front end 208. In one embodiment the front end 208 coupleswith a scheduler 210, which is configured to distribute commands orother work items to a processing cluster array 212. In one embodimentthe scheduler 210 ensures that the processing cluster array 212 isproperly configured and in a valid state before tasks are distributed tothe processing clusters of the processing cluster array 212. In oneembodiment the scheduler 210 is implemented via firmware logic executingon a microcontroller. The scheduler 210 cab be a microcontrollerimplemented scheduler that is configurable to perform complex schedulingand work distribution operations at coarse and fine granularity,enabling rapid preemption and context switching of threads executing onthe processing cluster array 212. In one embodiment, the host softwarecan prove workloads for scheduling on the processing cluster array 212via one of multiple graphics processing doorbells. The workloads canthen be automatically distributed across the processing cluster array212 by the scheduler 210 logic within the scheduler microcontroller.

The processing cluster array 212 can include up to “N” processingclusters (e.g., cluster 214A, cluster 214B, through cluster 214N). Eachcluster 214A-214N of the processing cluster array 212 can execute alarge number of concurrent threads. The scheduler 210 can allocate workto the clusters 214A-214N of the processing cluster array 212 usingvarious scheduling and/or work distribution algorithms, which may varydepending on the workload arising for each type of program orcomputation. The scheduling can be handled dynamically by the scheduler210, or can be assisted in part by compiler logic during compilation ofprogram logic configured for execution by the processing cluster array212. In one embodiment, different clusters 214A-214N of the processingcluster array 212 can be allocated for processing different types ofprograms or for performing different types of computations.

The processing cluster array 212 can be configured to perform varioustypes of parallel processing operations. In one embodiment theprocessing cluster array 212 is configured to perform general-purposeparallel compute operations. For example, the processing cluster array212 can include logic to execute processing tasks including filtering ofvideo and/or audio data, performing modeling operations, includingphysics operations, and performing data transformations.

In one embodiment the processing cluster array 212 is configured toperform parallel graphics processing operations. In embodiments in whichthe parallel processor 200 is configured to perform graphics processingoperations, the processing cluster array 212 can include additionallogic to support the execution of such graphics processing operations,including, but not limited to texture sampling logic to perform textureoperations, as well as tessellation logic and other vertex processinglogic. Additionally, the processing cluster array 212 can be configuredto execute graphics processing related shader programs such as, but notlimited to vertex shaders, tessellation shaders, geometry shaders, andpixel shaders. The parallel processing unit 202 can transfer data fromsystem memory via the I/O unit 204 for processing. During processing thetransferred data can be stored to on-chip memory (e.g., parallelprocessor memory 222) during processing, then written back to systemmemory.

In one embodiment, when the parallel processing unit 202 is used toperform graphics processing, the scheduler 210 can be configured todivide the processing workload into approximately equal sized tasks, tobetter enable distribution of the graphics processing operations tomultiple clusters 214A-214N of the processing cluster array 212. In someembodiments, portions of the processing cluster array 212 can beconfigured to perform different types of processing. For example a firstportion may be configured to perform vertex shading and topologygeneration, a second portion may be configured to perform tessellationand geometry shading, and a third portion may be configured to performpixel shading or other screen space operations, to produce a renderedimage for display. Intermediate data produced by one or more of theclusters 214A-214N may be stored in buffers to allow the intermediatedata to be transmitted between clusters 214A-214N for furtherprocessing.

During operation, the processing cluster array 212 can receiveprocessing tasks to be executed via the scheduler 210, which receivescommands defining processing tasks from front end 208. For graphicsprocessing operations, processing tasks can include indices of data tobe processed, e.g., surface (patch) data, primitive data, vertex data,and/or pixel data, as well as state parameters and commands defining howthe data is to be processed (e.g., what program is to be executed). Thescheduler 210 may be configured to fetch the indices corresponding tothe tasks or may receive the indices from the front end 208. The frontend 208 can be configured to ensure the processing cluster array 212 isconfigured to a valid state before the workload specified by incomingcommand buffers (e.g., batch-buffers, push buffers, etc.) is initiated.

Each of the one or more instances of the parallel processing unit 202can couple with parallel processor memory 222. The parallel processormemory 222 can be accessed via the memory crossbar 216, which canreceive memory requests from the processing cluster array 212 as well asthe I/O unit 204. The memory crossbar 216 can access the parallelprocessor memory 222 via a memory interface 218. The memory interface218 can include multiple partition units (e.g., partition unit 220A,partition unit 220B, through partition unit 220N) that can each coupleto a portion (e.g., memory unit) of parallel processor memory 222. Inone implementation the number of partition units 220A-220N is configuredto be equal to the number of memory units, such that a first partitionunit 220A has a corresponding first memory unit 224A, a second partitionunit 220B has a corresponding memory unit 224B, and an Nth partitionunit 220N has a corresponding Nth memory unit 224N. In otherembodiments, the number of partition units 220A-220N may not be equal tothe number of memory devices.

In various embodiments, the memory units 224A-224N can include varioustypes of memory devices, including dynamic random access memory (DRAM)or graphics random access memory, such as synchronous graphics randomaccess memory (SGRAM), including graphics double data rate (GDDR)memory. In one embodiment, the memory units 224A-224N may also include3D stacked memory, including but not limited to high bandwidth memory(HBM). Persons skilled in the art will appreciate that the specificimplementation of the memory units 224A-224N can vary, and can beselected from one of various conventional designs. Render targets, suchas frame buffers or texture maps may be stored across the memory units224A-224N, allowing partition units 220A-220N to write portions of eachrender target in parallel to efficiently use the available bandwidth ofparallel processor memory 222. In some embodiments, a local instance ofthe parallel processor memory 222 may be excluded in favor of a unifiedmemory design that utilizes system memory in conjunction with localcache memory.

In one embodiment, any one of the clusters 214A-214N of the processingcluster array 212 can process data that will be written to any of thememory units 224A-224N within parallel processor memory 222. The memorycrossbar 216 can be configured to transfer the output of each cluster214A-214N to any partition unit 220A-220N or to another cluster214A-214N, which can perform additional processing operations on theoutput. Each cluster 214A-214N can communicate with the memory interface218 through the memory crossbar 216 to read from or write to variousexternal memory devices. In one embodiment the memory crossbar 216 has aconnection to the memory interface 218 to communicate with the I/O unit204, as well as a connection to a local instance of the parallelprocessor memory 222, enabling the processing units within the differentprocessing clusters 214A-214N to communicate with system memory or othermemory that is not local to the parallel processing unit 202. In oneembodiment the memory crossbar 216 can use virtual channels to separatetraffic streams between the clusters 214A-214N and the partition units220A-220N.

While a single instance of the parallel processing unit 202 isillustrated within the parallel processor 200, any number of instancesof the parallel processing unit 202 can be included. For example,multiple instances of the parallel processing unit 202 can be providedon a single add-in card, or multiple add-in cards can be interconnected.The different instances of the parallel processing unit 202 can beconfigured to inter-operate even if the different instances havedifferent numbers of processing cores, different amounts of localparallel processor memory, and/or other configuration differences. Forexample, in one embodiment some instances of the parallel processingunit 202 can include higher precision floating point units relative toother instances. Systems incorporating one or more instances of theparallel processing unit 202 or the parallel processor 200 can beimplemented in a variety of configurations and form factors, includingbut not limited to desktop, laptop, or handheld personal computers,servers, workstations, game consoles, and/or embedded systems.

FIG. 2B is a block diagram of a partition unit 220, according to anembodiment. In one embodiment the partition unit 220 is an instance ofone of the partition units 220A-220N of FIG. 2A. As illustrated, thepartition unit 220 includes an L2 cache 221, a frame buffer interface225, and a ROP 226 (raster operations unit). The L2 cache 221 is aread/write cache that is configured to perform load and store operationsreceived from the memory crossbar 216 and ROP 226. Read misses andurgent write-back requests are output by L2 cache 221 to frame bufferinterface 225 for processing. Updates can also be sent to the framebuffer via the frame buffer interface 225 for processing. In oneembodiment the frame buffer interface 225 interfaces with one of thememory units in parallel processor memory, such as the memory units224A-224N of FIG. 2A (e.g., within parallel processor memory 222).

In graphics applications, the ROP 226 is a processing unit that performsraster operations such as stencil, z test, blending, and the like. TheROP 226 then outputs processed graphics data that is stored in graphicsmemory. In some embodiments the ROP 226 includes compression logic tocompress depth or color data that is written to memory and decompressdepth or color data that is read from memory. The compression logic canbe lossless compression logic that makes use of one or more of multiplecompression algorithms. The type of compression that is performed by theROP 226 can vary based on the statistical characteristics of the data tobe compressed. For example, in one embodiment, delta color compressionis performed on depth and color data on a per-tile basis.

In some embodiments, the ROP 226 is included within each processingcluster (e.g., cluster 214A-214N of FIG. 2A) instead of within thepartition unit 220. In such embodiment, read and write requests forpixel data are transmitted over the memory crossbar 216 instead of pixelfragment data. The processed graphics data may be displayed on a displaydevice, such as one of the one or more display device(s) 110 of FIG. 1,routed for further processing by the processor(s) 102, or routed forfurther processing by one of the processing entities within the parallelprocessor 200 of FIG. 2A.

FIG. 2C is a block diagram of a processing cluster 214 within a parallelprocessing unit, according to an embodiment. In one embodiment theprocessing cluster is an instance of one of the processing clusters214A-214N of FIG. 2A. The processing cluster 214 can be configured toexecute many threads in parallel, where the term “thread” refers to aninstance of a particular program executing on a particular set of inputdata. In some embodiments, single-instruction, multiple-data (SIMD)instruction issue techniques are used to support parallel execution of alarge number of threads without providing multiple independentinstruction units. In other embodiments, single-instruction,multiple-thread (SIMT) techniques are used to support parallel executionof a large number of generally synchronized threads, using a commoninstruction unit configured to issue instructions to a set of processingengines within each one of the processing clusters. Unlike a SIMDexecution regime, where all processing engines typically executeidentical instructions, SIMT execution allows different threads to morereadily follow divergent execution paths through a given thread program.Persons skilled in the art will understand that a SIMD processing regimerepresents a functional subset of a SIMT processing regime.

Operation of the processing cluster 214 can be controlled via a pipelinemanager 232 that distributes processing tasks to SIMT parallelprocessors. The pipeline manager 232 receives instructions from thescheduler 210 of FIG. 2A and manages execution of those instructions viaa graphics multiprocessor 234 and/or a texture unit 236. The illustratedgraphics multiprocessor 234 is an exemplary instance of a SIMT parallelprocessor. However, various types of SIMT parallel processors ofdiffering architectures may be included within the processing cluster214. One or more instances of the graphics multiprocessor 234 can beincluded within a processing cluster 214. The graphics multiprocessor234 can process data and a data crossbar 240 can be used to distributethe processed data to one of multiple possible destinations, includingother shader units. The pipeline manager 232 can facilitate thedistribution of processed data by specifying destinations for processeddata to be distributed via the data crossbar 240.

Each graphics multiprocessor 234 within the processing cluster 214 caninclude an identical set of functional execution logic (e.g., arithmeticlogic units, load-store units, etc.). The functional execution logic canbe configured in a pipelined manner in which new instructions can beissued before previous instructions are complete. The functionalexecution logic supports a variety of operations including integer andfloating point arithmetic, comparison operations, Boolean operations,bit-shifting, and computation of various algebraic functions. In oneembodiment the same functional-unit hardware can be leveraged to performdifferent operations and any combination of functional units may bepresent.

The instructions transmitted to the processing cluster 214 constitutes athread. A set of threads executing across the set of parallel processingengines is a thread group. A thread group executes the same program ondifferent input data. Each thread within a thread group can be assignedto a different processing engine within a graphics multiprocessor 234. Athread group may include fewer threads than the number of processingengines within the graphics multiprocessor 234. When a thread groupincludes fewer threads than the number of processing engines, one ormore of the processing engines may be idle during cycles in which thatthread group is being processed. A thread group may also include morethreads than the number of processing engines within the graphicsmultiprocessor 234. When the thread group includes more threads than thenumber of processing engines within the graphics multiprocessor 234,processing can be performed over consecutive clock cycles. In oneembodiment multiple thread groups can be executed concurrently on agraphics multiprocessor 234.

In one embodiment the graphics multiprocessor 234 includes an internalcache memory to perform load and store operations. In one embodiment,the graphics multiprocessor 234 can forego an internal cache and use acache memory (e.g., L1 cache 248) within the processing cluster 214.Each graphics multiprocessor 234 also has access to L2 caches within thepartition units (e.g., partition units 220A-220N of FIG. 2A) that areshared among all processing clusters 214 and may be used to transferdata between threads. The graphics multiprocessor 234 may also accessoff-chip global memory, which can include one or more of local parallelprocessor memory and/or system memory. Any memory external to theparallel processing unit 202 may be used as global memory. Embodimentsin which the processing cluster 214 includes multiple instances of thegraphics multiprocessor 234 can share common instructions and data,which may be stored in the L1 cache 248.

Each processing cluster 214 may include an MMU 245 (memory managementunit) that is configured to map virtual addresses into physicaladdresses. In other embodiments, one or more instances of the MMU 245may reside within the memory interface 218 of FIG. 2A. The MMU 245includes a set of page table entries (PTEs) used to map a virtualaddress to a physical address of a tile and optionally a cache lineindex. The MMU 245 may include address translation lookaside buffers(TLB) or caches that may reside within the graphics multiprocessor 234or the L1 cache or processing cluster 214. The physical address isprocessed to distribute surface data access locality to allow efficientrequest interleaving among partition units. The cache line index may beused to determine whether a request for a cache line is a hit or miss.

In graphics and computing applications, a processing cluster 214 may beconfigured such that each graphics multiprocessor 234 is coupled to atexture unit 236 for performing texture mapping operations, e.g.,determining texture sample positions, reading texture data, andfiltering the texture data. Texture data is read from an internaltexture L1 cache (not shown) or in some embodiments from the L1 cachewithin graphics multiprocessor 234 and is fetched from an L2 cache,local parallel processor memory, or system memory, as needed. Eachgraphics multiprocessor 234 outputs processed tasks to the data crossbar240 to provide the processed task to another processing cluster 214 forfurther processing or to store the processed task in an L2 cache, localparallel processor memory, or system memory via the memory crossbar 216.A preROP 242 (pre-raster operations unit) is configured to receive datafrom graphics multiprocessor 234, direct data to ROP units, which may belocated with partition units as described herein (e.g., partition units220A-220N of FIG. 2A). The preROP 242 unit can perform optimizations forcolor blending, organize pixel color data, and perform addresstranslations.

It will be appreciated that the core architecture described herein isillustrative and that variations and modifications are possible. Anynumber of processing units, e.g., graphics multiprocessor 234, textureunits 236, preROPs 242, etc., may be included within a processingcluster 214. Further, while only one processing cluster 214 is shown, aparallel processing unit as described herein may include any number ofinstances of the processing cluster 214. In one embodiment, eachprocessing cluster 214 can be configured to operate independently ofother processing clusters 214 using separate and distinct processingunits, L1 caches, etc.

FIG. 2D shows a graphics multiprocessor 234, according to oneembodiment. In such embodiment the graphics multiprocessor 234 coupleswith the pipeline manager 232 of the processing cluster 214. Thegraphics multiprocessor 234 has an execution pipeline including but notlimited to an instruction cache 252, an instruction unit 254, an addressmapping unit 256, a register file 258, one or more general purposegraphics processing unit (GPGPU) cores 262, and one or more load/storeunits 266. The GPGPU cores 262 and load/store units 266 are coupled withcache memory 272 and shared memory 270 via a memory and cacheinterconnect 268.

In one embodiment, the instruction cache 252 receives a stream ofinstructions to execute from the pipeline manager 232. The instructionsare cached in the instruction cache 252 and dispatched for execution bythe instruction unit 254. The instruction unit 254 can dispatchinstructions as thread groups (e.g., warps), with each thread of thethread group assigned to a different execution unit within GPGPU core262. An instruction can access any of a local, shared, or global addressspace by specifying an address within a unified address space. Theaddress mapping unit 256 can be used to translate addresses in theunified address space into a distinct memory address that can beaccessed by the load/store units 266.

The register file 258 provides a set of registers for the functionalunits of the graphics multiprocessor 234. The register file 258 providestemporary storage for operands connected to the data paths of thefunctional units (e.g., GPGPU cores 262, load/store units 266) of thegraphics multiprocessor 234. In one embodiment, the register file 258 isdivided between each of the functional units such that each functionalunit is allocated a dedicated portion of the register file 258. In oneembodiment, the register file 258 is divided between the different warpsbeing executed by the graphics multiprocessor 234.

The GPGPU cores 262 can each include floating point units (FPUs) and/orinteger arithmetic logic units (ALUs) that are used to executeinstructions of the graphics multiprocessor 234. The GPGPU cores 262 canbe similar in architecture or can differ in architecture, according toembodiments. For example in one embodiment, a first portion of the GPGPUcores 262 include a single precision FPU and an integer ALU while asecond portion of the GPGPU cores include a double precision FPU. In oneembodiment the FPUs can implement the IEEE 754-2008 standard forfloating point arithmetic or enable variable precision floating pointarithmetic. The graphics multiprocessor 234 can additionally include oneor more fixed function or special function units to perform specificfunctions such as copy rectangle or pixel blending operations. In oneembodiment one or more of the GPGPU cores can also include fixed orspecial function logic.

In one embodiment the GPGPU cores 262 include SIMD logic capable ofperforming a single instruction on multiple sets of data. In oneembodiment GPGPU cores 262 can physically execute SIMD4, SIMD8, andSIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32instructions. The SIMD instructions for the GPGPU cores can be generatedat compile time by a shader compiler or automatically generated whenexecuting programs written and compiled for single program multiple data(SPMD) or SIMT architectures. Multiple threads of a program configuredfor the SIMT execution model can be executed via a single SIMDinstruction. For example and in one embodiment, eight SIMT threads thatperform the same or similar operations can be executed in parallel via asingle SIMD8 logic unit.

The memory and cache interconnect 268 is an interconnect network thatconnects each of the functional units of the graphics multiprocessor 234to the register file 258 and to the shared memory 270. In oneembodiment, the memory and cache interconnect 268 is a crossbarinterconnect that allows the load/store unit 266 to implement load andstore operations between the shared memory 270 and the register file258. The register file 258 can operate at the same frequency as theGPGPU cores 262, thus data transfer between the GPGPU cores 262 and theregister file 258 is very low latency. The shared memory 270 can be usedto enable communication between threads that execute on the functionalunits within the graphics multiprocessor 234. The cache memory 272 canbe used as a data cache for example, to cache texture data communicatedbetween the functional units and the texture unit 236. The shared memory270 can also be used as a program managed cached. Threads executing onthe GPGPU cores 262 can programmatically store data within the sharedmemory in addition to the automatically cached data that is storedwithin the cache memory 272.

FIG. 3A-3B illustrate additional graphics multiprocessors, according toembodiments. The illustrated graphics multiprocessors 325, 350 arevariants of the graphics multiprocessor 234 of FIG. 2C. The illustratedgraphics multiprocessors 325, 350 can be configured as a streamingmultiprocessor (SM) capable of simultaneous execution of a large numberof execution threads.

FIG. 3A shows a graphics multiprocessor 325 according to an additionalembodiment. The graphics multiprocessor 325 includes multiple additionalinstances of execution resource units relative to the graphicsmultiprocessor 234 of FIG. 2D. For example, the graphics multiprocessor325 can include multiple instances of the instruction unit 332A-332B,register file 334A-334B, and texture unit(s) 344A-344B. The graphicsmultiprocessor 325 also includes multiple sets of graphics or computeexecution units (e.g., GPGPU core 336A-336B, GPGPU core 337A-337B, GPGPUcore 338A-338B) and multiple sets of load/store units 340A-340B. In oneembodiment the execution resource units have a common instruction cache330, texture and/or data cache memory 342, and shared memory 346.

The various components can communicate via an interconnect fabric 327.In one embodiment the interconnect fabric 327 includes one or morecrossbar switches to enable communication between the various componentsof the graphics multiprocessor 325. In one embodiment the interconnectfabric 327 is a separate, high-speed network fabric layer upon whicheach component of the graphics multiprocessor 325 is stacked. Thecomponents of the graphics multiprocessor 325 communicate with remotecomponents via the interconnect fabric 327. For example, the GPGPU cores336A-336B, 337A-337B, and 3378A-338B can each communicate with sharedmemory 346 via the interconnect fabric 327. The interconnect fabric 327can arbitrate communication within the graphics multiprocessor 325 toensure a fair bandwidth allocation between components.

FIG. 3B shows a graphics multiprocessor 350 according to an additionalembodiment. The graphics processor includes multiple sets of executionresources 356A-356D, where each set of execution resource includesmultiple instruction units, register files, GPGPU cores, and load storeunits, as illustrated in FIG. 2D and FIG. 3A. The execution resources356A-356D can work in concert with texture unit(s) 360A-360D for textureoperations, while sharing an instruction cache 354, and shared memory362. In one embodiment the execution resources 356A-356D can share aninstruction cache 354 and shared memory 362, as well as multipleinstances of a texture and/or data cache memory 358A-358B. The variouscomponents can communicate via an interconnect fabric 352 similar to theinterconnect fabric 327 of FIG. 3A.

Persons skilled in the art will understand that the architecturedescribed in FIGS. 1, 2A-2D, and 3A-3B are descriptive and not limitingas to the scope of the present embodiments. Thus, the techniquesdescribed herein may be implemented on any properly configuredprocessing unit, including, without limitation, one or more mobileapplication processors, one or more desktop or server central processingunits (CPUs) including multi-core CPUs, one or more parallel processingunits, such as the parallel processing unit 202 of FIG. 2A, as well asone or more graphics processors or special purpose processing units,without departure from the scope of the embodiments described herein.

In some embodiments a parallel processor or GPGPU as described herein iscommunicatively coupled to host/processor cores to accelerate graphicsoperations, machine-learning operations, pattern analysis operations,and various general purpose GPU (GPGPU) functions. The GPU may becommunicatively coupled to the host processor/cores over a bus or otherinterconnect (e.g., a high speed interconnect such as PCIe or NVLink).In other embodiments, the GPU may be integrated on the same package orchip as the cores and communicatively coupled to the cores over aninternal processor bus/interconnect (i.e., internal to the package orchip). Regardless of the manner in which the GPU is connected, theprocessor cores may allocate work to the GPU in the form of sequences ofcommands/instructions contained in a work descriptor. The GPU then usesdedicated circuitry/logic for efficiently processing thesecommands/instructions.

Techniques for GPU to Host Processor Interconnection

FIG. 4A illustrates an exemplary architecture in which a plurality ofGPUs 410-413 are communicatively coupled to a plurality of multi-coreprocessors 405-406 over high-speed links 440A-440D (e.g., buses,point-to-point interconnects, etc.). In one embodiment, the high-speedlinks 440A-440D support a communication throughput of 4 GB/s, 30 GB/s,80 GB/s or higher, depending on the implementation. Various interconnectprotocols may be used including, but not limited to, PCIe 4.0 or 5.0 andNVLink 2.0. However, the underlying principles of the invention are notlimited to any particular communication protocol or throughput.

In addition, in one embodiment, two or more of the GPUs 410-413 areinterconnected over high-speed links 442A-442B, which may be implementedusing the same or different protocols/links than those used forhigh-speed links 440A-440D. Similarly, two or more of the multi-coreprocessors 405-406 may be connected over high speed link 443 which maybe symmetric multi-processor (SMP) buses operating at 20 GB/s, 30 GB/s,120 GB/s or higher. Alternatively, all communication between the varioussystem components shown in FIG. 4A may be accomplished using the sameprotocols/links (e.g., over a common interconnection fabric). Asmentioned, however, the underlying principles of the invention are notlimited to any particular type of interconnect technology.

In one embodiment, each multi-core processor 405-406 is communicativelycoupled to a processor memory 401-402, via memory interconnects430A-430B, respectively, and each GPU 410-413 is communicatively coupledto GPU memory 420-423 over GPU memory interconnects 450A-450D,respectively. The memory interconnects 430A-430B and 450A-450D mayutilize the same or different memory access technologies. By way ofexample, and not limitation, the processor memories 401-402 and GPUmemories 420-423 may be volatile memories such as dynamic random accessmemories (DRAMs) (including stacked DRAMs), Graphics DDR SDRAM (GDDR)(e.g., GDDR5, GDDR6), or High Bandwidth Memory (HBM) and/or may benon-volatile memories such as 3D XPoint or Nano-Ram. In one embodiment,some portion of the memories may be volatile memory and another portionmay be non-volatile memory (e.g., using a two-level memory (2LM)hierarchy).

As described below, although the various processors 405-406 and GPUs410-413 may be physically coupled to a particular memory 401-402,420-423, respectively, a unified memory architecture may be implementedin which the same virtual system address space (also referred to as the“effective address” space) is distributed among all of the variousphysical memories. For example, processor memories 401-402 may eachcomprise 64 GB of the system memory address space and GPU memories420-423 may each comprise 32 GB of the system memory address space(resulting in a total of 256 GB addressable memory in this example).

FIG. 4B illustrates additional details for an interconnection between amulti-core processor 407 and a graphics acceleration module 446 inaccordance with one embodiment. The graphics acceleration module 446 mayinclude one or more GPU chips integrated on a line card which is coupledto the processor 407 via the high-speed link 440. Alternatively, thegraphics acceleration module 446 may be integrated on the same packageor chip as the processor 407.

The illustrated processor 407 includes a plurality of cores 460A-460D,each with a translation lookaside buffer 461A-461D and one or morecaches 462A-462D. The cores may include various other components forexecuting instructions and processing data which are not illustrated toavoid obscuring the underlying principles of the invention (e.g.,instruction fetch units, branch prediction units, decoders, executionunits, reorder buffers, etc.). The caches 462A-462D may comprise level 1(L1) and level 2 (L2) caches. In addition, one or more shared caches 456may be included in the caching hierarchy and shared by sets of the cores460A-460D. For example, one embodiment of the processor 407 includes 24cores, each with its own L1 cache, twelve shared L2 caches, and twelveshared L3 caches. In this embodiment, one of the L2 and L3 caches areshared by two adjacent cores. The processor 407 and the graphicsaccelerator integration module 446 connect with system memory 441, whichmay include processor memories 401-402.

Coherency is maintained for data and instructions stored in the variouscaches 462A-462D, 456 and system memory 441 via inter-core communicationover a coherence bus 464. For example, each cache may have cachecoherency logic/circuitry associated therewith to communicate to overthe coherence bus 464 in response to detected reads or writes toparticular cache lines. In one implementation, a cache snooping protocolis implemented over the coherence bus 464 to snoop cache accesses. Cachesnooping/coherency techniques are well understood by those of skill inthe art and will not be described in detail here to avoid obscuring theunderlying principles of the invention.

In one embodiment, a proxy circuit 425 communicatively couples thegraphics acceleration module 446 to the coherence bus 464, allowing thegraphics acceleration module 446 to participate in the cache coherenceprotocol as a peer of the cores. In particular, an interface 435provides connectivity to the proxy circuit 425 over high-speed link 440(e.g., a PCIe bus, NVLink, etc.) and an interface 437 connects thegraphics acceleration module 446 to the high-speed link 440.

In one implementation, an accelerator integration circuit 436 providescache management, memory access, context management, and interruptmanagement services on behalf of a plurality of graphics processingengines 431, 432, N of the graphics acceleration module 446. Thegraphics processing engines 431, 432, N may each comprise a separategraphics processing unit (GPU). Alternatively, the graphics processingengines 431, 432, N may comprise different types of graphics processingengines within a GPU such as graphics execution units, media processingengines (e.g., video encoders/decoders), samplers, and blit engines. Inother words, the graphics acceleration module may be a GPU with aplurality of graphics processing engines 431-432, N or the graphicsprocessing engines 431-432, N may be individual GPUs integrated on acommon package, line card, or chip.

In one embodiment, the accelerator integration circuit 436 includes amemory management unit (MMU) 439 for performing various memorymanagement functions such as virtual-to-physical memory translations(also referred to as effective-to-real memory translations) and memoryaccess protocols for accessing system memory 441. The MMU 439 may alsoinclude a translation lookaside buffer (TLB) (not shown) for caching thevirtual/effective to physical/real address translations. In oneembodiment, the accelerator integration circuit 436 includes a fetchunit 491 to fetch commands, instructions, work descriptors, etc., thatdefine operations to be performed. In one implementation, a cache 438stores commands and data for efficient access by the graphics processingengines 431-432, N. In one embodiment, the data stored in cache 438 andgraphics memories 433-434, M is kept coherent with the core caches462A-462D, 456 and system memory 411. As mentioned, this may beaccomplished via proxy circuit 425 which takes part in the cachecoherency mechanism on behalf of cache 438 and memories 433-434, M(e.g., sending updates to the cache 438 related tomodifications/accesses of cache lines on processor caches 462A-462D, 456and receiving updates from the cache 438).

A set of registers 445 store context data for threads executed by thegraphics processing engines 431-432, N and a context management circuit448 manages the thread contexts. For example, the context managementcircuit 448 may perform save and restore operations to save and restorecontexts of the various threads during contexts switches (e.g., where afirst thread is saved and a second thread is stored so that the secondthread can be execute by a graphics processing engine). For example, ona context switch, the context management circuit 448 may store currentregister values to a designated region in memory (e.g., identified by acontext pointer). It may then restore the register values when returningto the context. In one embodiment, an interrupt management circuit 447receives and processes interrupts received from system devices.

In one implementation, virtual/effective addresses from a graphicsprocessing engine 431 are translated to real/physical addresses insystem memory 411 by the MMU 439. One embodiment of the acceleratorintegration circuit 436 supports multiple (e.g., 4, 8, 16) graphicsaccelerator modules 446 and/or other accelerator devices. The graphicsaccelerator module 446 may be dedicated to a single application executedon the processor 407 or may be shared between multiple applications. Inone embodiment, a virtualized graphics execution environment ispresented in which the resources of the graphics processing engines431-432, N are shared with multiple applications or virtual machines(VMs). The resources may be subdivided into “slices” which are allocatedto different VMs and/or applications based on the processingrequirements and priorities associated with the VMs and/or applications.

Thus, the accelerator integration circuit acts as a bridge to the systemfor the graphics acceleration module 446 and provides addresstranslation and system memory cache services. In addition, theaccelerator integration circuit 436 may provide virtualizationfacilities for the host processor to manage virtualization of thegraphics processing engines, interrupts, and memory management.

Because hardware resources of the graphics processing engines 431-432, Nare mapped explicitly to the real address space seen by the hostprocessor 407, any host processor can address these resources directlyusing an effective address value. One function of the acceleratorintegration circuit 436, in one embodiment, is the physical separationof the graphics processing engines 431-432, N so that they appear to thesystem as independent units.

As mentioned, in the illustrated embodiment, one or more graphicsmemories 433-434, M are coupled to each of the graphics processingengines 431-432, N, respectively. The graphics memories 433-434, M storeinstructions and data being processed by each of the graphics processingengines 431-432, N. The graphics memories 433-434, M may be volatilememories such as DRAMs (including stacked DRAMs), GDDR memory (e.g.,GDDR5, GDDR6), or HBM, and/or may be non-volatile memories such as 3DXPoint or Nano-Ram.

In one embodiment, to reduce data traffic over the high-speed link 440,biasing techniques are used to ensure that the data stored in graphicsmemories 433-434, M is data which will be used most frequently by thegraphics processing engines 431-432, N and preferably not used by thecores 460A-460D (at least not frequently). Similarly, the biasingmechanism attempts to keep data needed by the cores (and preferably notthe graphics processing engines 431-432, N) within the caches 462A-462D,456 of the cores and system memory 411.

FIG. 4C illustrates another embodiment in which the acceleratorintegration circuit 436 is integrated within the processor 407. In thisembodiment, the graphics processing engines 431-432, N communicatedirectly over the high-speed link 440 to the accelerator integrationcircuit 436 via interface 437 and interface 435 (which, again, may beutilize any form of bus or interface protocol). The acceleratorintegration circuit 436 may perform the same operations as thosedescribed with respect to FIG. 4B, but potentially at a higherthroughput given its close proximity to the coherency bus 464 and caches462A-462D, 456.

One embodiment supports different programming models including adedicated-process programming model (no graphics acceleration modulevirtualization) and shared programming models (with virtualization). Thelatter may include programming models which are controlled by theaccelerator integration circuit 436 and programming models which arecontrolled by the graphics acceleration module 446.

In one embodiment of the dedicated process model, graphics processingengines 431-432, N are dedicated to a single application or processunder a single operating system. The single application can funnel otherapplication requests to the graphics engines 431-432, N, providingvirtualization within a VM/partition.

In the dedicated-process programming models, the graphics processingengines 431-432, N, may be shared by multiple VM/application partitions.The shared models require a system hypervisor to virtualize the graphicsprocessing engines 431-432, N to allow access by each operating system.For single-partition systems without a hypervisor, the graphicsprocessing engines 431-432, N are owned by the operating system. In bothcases, the operating system can virtualize the graphics processingengines 431-432, N to provide access to each process or application.

For the shared programming model, the graphics acceleration module 446or an individual graphics processing engine 431-432, N selects a processelement using a process handle. In one embodiment, process elements arestored in system memory 411 and are addressable using the effectiveaddress to real address translation techniques described herein. Theprocess handle may be an implementation-specific value provided to thehost process when registering its context with the graphics processingengine 431-432, N (that is, calling system software to add the processelement to the process element linked list). The lower 16-bits of theprocess handle may be the offset of the process element within theprocess element linked list.

FIG. 4D illustrates an exemplary accelerator integration slice 490. Asused herein, a “slice” comprises a specified portion of the processingresources of the accelerator integration circuit 436. Applicationeffective address space 482 within system memory 411 stores processelements 483. In one embodiment, the process elements 483 are stored inresponse to GPU invocations 481 from applications 480 executed on theprocessor 407. A process element 483 contains the process state for thecorresponding application 480. A work descriptor (WD) 484 contained inthe process element 483 can be a single job requested by an applicationor may contain a pointer to a queue of jobs. In the latter case, the WD484 is a pointer to the job request queue in the application's addressspace 482.

The graphics acceleration module 446 and/or the individual graphicsprocessing engines 431-432, N can be shared by all or a subset of theprocesses in the system. Embodiments of the invention include aninfrastructure for setting up the process state and sending a WD 484 toa graphics acceleration module 446 to start a job in a virtualizedenvironment.

In one implementation, the dedicated-process programming model isimplementation-specific. In this model, a single process owns thegraphics acceleration module 446 or an individual graphics processingengine 431. Because the graphics acceleration module 446 is owned by asingle process, the hypervisor initializes the accelerator integrationcircuit 436 for the owning partition and the operating systeminitializes the accelerator integration circuit 436 for the owningprocess at the time when the graphics acceleration module 446 isassigned.

In operation, a WD fetch unit 491 in the accelerator integration slice490 fetches the next WD 484 which includes an indication of the work tobe done by one of the graphics processing engines of the graphicsacceleration module 446. Data from the WD 484 may be stored in registers445 and used by the MMU 439, interrupt management circuit 447 and/orcontext management circuit 448 as illustrated. For example, oneembodiment of the MMU 439 includes segment/page walk circuitry foraccessing segment/page tables 486 within the OS virtual address space485. The interrupt management circuit 447 may process interrupt events492 received from the graphics acceleration module 446. When performinggraphics operations, an effective address 493 generated by a graphicsprocessing engine 431-432, N is translated to a real address by the MMU439.

In one embodiment, the same set of registers 445 are duplicated for eachgraphics processing engine 431-432, N and/or graphics accelerationmodule 446 and may be initialized by the hypervisor or operating system.Each of these duplicated registers may be included in an acceleratorintegration slice 490. Exemplary registers that may be initialized bythe hypervisor are shown in Table 1.

TABLE 1 Hypervisor Initialized Registers 1 Slice Control Register 2 RealAddress (RA) Scheduled Processes Area Pointer 3 Authority Mask OverrideRegister 4 Interrupt Vector Table Entry Offset 5 Interrupt Vector TableEntry Limit 6 State Register 7 Logical Partition ID 8 Real address (RA)Hypervisor Accelerator Utilization Record Pointer 9 Storage DescriptionRegister

Exemplary registers that may be initialized by the operating system areshown in Table 2.

TABLE 2 Operating System Initialized Registers 1 Process and ThreadIdentification 2 Effective Address (EA) Context Save/Restore Pointer 3Virtual Address (VA) Accelerator Utilization Record Pointer 4 VirtualAddress (VA) Storage Segment Table Pointer 5 Authority Mask 6 Workdescriptor

In one embodiment, each WD 484 is specific to a particular graphicsacceleration module 446 and/or graphics processing engine 431-432, N. Itcontains all the information a graphics processing engine 431-432, Nrequires to do its work or it can be a pointer to a memory locationwhere the application has set up a command queue of work to becompleted.

FIG. 4E illustrates additional details for one embodiment of a sharedmodel. This embodiment includes a hypervisor real address space 498 inwhich a process element list 499 is stored. The hypervisor real addressspace 498 is accessible via a hypervisor 496 which virtualizes thegraphics acceleration module engines for the operating system 495.

The shared programming models allow for all or a subset of processesfrom all or a subset of partitions in the system to use a graphicsacceleration module 446. There are two programming models where thegraphics acceleration module 446 is shared by multiple processes andpartitions: time-sliced shared and graphics directed shared.

In this model, the system hypervisor 496 owns the graphics accelerationmodule 446 and makes its function available to all operating systems495. For a graphics acceleration module 446 to support virtualization bythe system hypervisor 496, the graphics acceleration module 446 mayadhere to the following requirements: 1) An application's job requestmust be autonomous (that is, the state does not need to be maintainedbetween jobs), or the graphics acceleration module 446 must provide acontext save and restore mechanism. 2) An application's job request isguaranteed by the graphics acceleration module 446 to complete in aspecified amount of time, including any translation faults, or thegraphics acceleration module 446 provides the ability to preempt theprocessing of the job. 3) The graphics acceleration module 446 must beguaranteed fairness between processes when operating in the directedshared programming model.

In one embodiment, for the shared model, the application 480 is requiredto make an operating system 495 system call with a graphics accelerationmodule 446 type, a work descriptor (WD), an authority mask register(AMR) value, and a context save/restore area pointer (CSRP). Thegraphics acceleration module 446 type describes the targetedacceleration function for the system call. The graphics accelerationmodule 446 type may be a system-specific value. The WD is formattedspecifically for the graphics acceleration module 446 and can be in theform of a graphics acceleration module 446 command, an effective addresspointer to a user-defined structure, an effective address pointer to aqueue of commands, or any other data structure to describe the work tobe done by the graphics acceleration module 446. In one embodiment, theAMR value is the AMR state to use for the current process. The valuepassed to the operating system is similar to an application setting theAMR. If the accelerator integration circuit 436 and graphicsacceleration module 446 implementations do not support a User AuthorityMask Override Register (UAMOR), the operating system may apply thecurrent UAMOR value to the AMR value before passing the AMR in thehypervisor call. The hypervisor 496 may optionally apply the currentAuthority Mask Override Register (AMOR) value before placing the AMRinto the process element 483. In one embodiment, the CSRP is one of theregisters 445 containing the effective address of an area in theapplication's address space 482 for the graphics acceleration module 446to save and restore the context state. This pointer is optional if nostate is required to be saved between jobs or when a job is preempted.The context save/restore area may be pinned system memory.

Upon receiving the system call, the operating system 495 may verify thatthe application 480 has registered and been given the authority to usethe graphics acceleration module 446. The operating system 495 thencalls the hypervisor 496 with the information shown in Table 3.

TABLE 3 OS to Hypervisor Call Parameters 1 A work descriptor (WD) 2 AnAuthority Mask Register (AMR) value (potentially masked). 3 An effectiveaddress (EA) Context Save/Restore Area Pointer (CSRP) 4 A process ID(PID) and optional thread ID (TID) 5 A virtual address (VA) acceleratorutilization record pointer (AURP) 6 The virtual address of the storagesegment table pointer (SSTP) 7 A logical interrupt service number (LISN)

Upon receiving the hypervisor call, the hypervisor 496 verifies that theoperating system 495 has registered and been given the authority to usethe graphics acceleration module 446. The hypervisor 496 then puts theprocess element 483 into the process element linked list for thecorresponding graphics acceleration module 446 type. The process elementmay include the information shown in Table 4.

TABLE 4 Process Element Information  1 A work descriptor (WD)  2 AnAuthority Mask Register (AMR) value (potentially masked).  3 Aneffective address (EA) Context Save/Restore Area Pointer (CSRP)  4 Aprocess ID (PID) and optional thread ID (TID)  5 A virtual address (VA)accelerator utilization record pointer (AURP)  6 The virtual address ofthe storage segment table pointer (SSTP)  7 A logical interrupt servicenumber (LISN)  8 Interrupt vector table, derived from the hypervisorcall parameters.  9 A state register (SR) value 10 A logical partitionID (LPID) 11 A real address (RA) hypervisor accelerator utilizationrecord pointer 12 The Storage Descriptor Register (SDR)

In one embodiment, the hypervisor initializes a plurality of acceleratorintegration slice 490 registers 445.

As illustrated in FIG. 4F, one embodiment of the invention employs aunified memory addressable via a common virtual memory address spaceused to access the physical processor memories 401-402 and GPU memories420-423. In this implementation, operations executed on the GPUs 410-413utilize the same virtual/effective memory address space to access theprocessors memories 401-402 and vice versa, thereby simplifyingprogrammability. In one embodiment, a first portion of thevirtual/effective address space is allocated to the processor memory401, a second portion to the second processor memory 402, a thirdportion to the GPU memory 420, and so on. The entire virtual/effectivememory space (sometimes referred to as the effective address space) isthereby distributed across each of the processor memories 401-402 andGPU memories 420-423, allowing any processor or GPU to access anyphysical memory with a virtual address mapped to that memory.

In one embodiment, bias/coherence management circuitry 494A-494E withinone or more of the MMUs 439A-439E ensures cache coherence between thecaches of the host processors (e.g., 405) and the GPUs 410-413 andimplements biasing techniques indicating the physical memories in whichcertain types of data should be stored. While multiple instances ofbias/coherence management circuitry 494A-494E are illustrated in FIG.4F, the bias/coherence circuitry may be implemented within the MMU ofone or more host processors 405 and/or within the acceleratorintegration circuit 436.

One embodiment allows GPU-attached memory 420-423 to be mapped as partof system memory, and accessed using shared virtual memory (SVM)technology, but without suffering the typical performance drawbacksassociated with full system cache coherence. The ability to GPU-attachedmemory 420-423 to be accessed as system memory without onerous cachecoherence overhead provides a beneficial operating environment for GPUoffload. This arrangement allows the host processor 405 software tosetup operands and access computation results, without the overhead oftradition I/O DMA data copies. Such traditional copies involve drivercalls, interrupts and memory mapped I/O (MMIO) accesses that are allinefficient relative to simple memory accesses. At the same time, theability to access GPU attached memory 420-423 without cache coherenceoverheads can be critical to the execution time of an offloadedcomputation. In cases with substantial streaming write memory traffic,for example, cache coherence overhead can significantly reduce theeffective write bandwidth seen by a GPU 410-413. The efficiency ofoperand setup, the efficiency of results access, and the efficiency ofGPU computation all play a role in determining the effectiveness of GPUoffload.

In one implementation, the selection of between GPU bias and hostprocessor bias is driven by a bias tracker data structure. A bias tablemay be used, for example, which may be a page-granular structure (i.e.,controlled at the granularity of a memory page) that includes 1 or 2bits per GPU-attached memory page. The bias table may be implemented ina stolen memory range of one or more GPU-attached memories 420-423, withor without a bias cache in the GPU 410-413 (e.g., to cachefrequently/recently used entries of the bias table). Alternatively, theentire bias table may be maintained within the GPU.

In one implementation, the bias table entry associated with each accessto the GPU-attached memory 420-423 is accessed prior the actual accessto the GPU memory, causing the following operations. First, localrequests from the GPU 410-413 that find their page in GPU bias areforwarded directly to a corresponding GPU memory 420-423. Local requestsfrom the GPU that find their page in host bias are forwarded to theprocessor 405 (e.g., over a high-speed link as discussed above). In oneembodiment, requests from the processor 405 that find the requested pagein host processor bias complete the request like a normal memory read.Alternatively, requests directed to a GPU-biased page may be forwardedto the GPU 410-413. The GPU may then transition the page to a hostprocessor bias if it is not currently using the page.

The bias state of a page can be changed either by a software-basedmechanism, a hardware-assisted software-based mechanism, or, for alimited set of cases, a purely hardware-based mechanism.

One mechanism for changing the bias state employs an API call (e.g.OpenCL), which, in turn, calls the GPU's device driver which, in turn,sends a message (or enqueues a command descriptor) to the GPU directingit to change the bias state and, for some transitions, perform a cacheflushing operation in the host. The cache flushing operation is requiredfor a transition from host processor 405 bias to GPU bias, but is notrequired for the opposite transition.

In one embodiment, cache coherency is maintained by temporarilyrendering GPU-biased pages uncacheable by the host processor 405. Toaccess these pages, the processor 405 may request access from the GPU410 which may or may not grant access right away, depending on theimplementation. Thus, to reduce communication between the processor 405and GPU 410 it is beneficial to ensure that GPU-biased pages are thosewhich are required by the GPU but not the host processor 405 and viceversa.

Graphics Processing Pipeline

FIG. 5 illustrates a graphics processing pipeline 500, according to anembodiment. In one embodiment a graphics processor can implement theillustrated graphics processing pipeline 500. The graphics processor canbe included within the parallel processing subsystems as describedherein, such as the parallel processor 200 of FIG. 2A, which, in oneembodiment, is a variant of the parallel processor(s) 112 of FIG. 1. Thevarious parallel processing systems can implement the graphicsprocessing pipeline 500 via one or more instances of the parallelprocessing unit (e.g., parallel processing unit 202 of FIG. 2A) asdescribed herein. For example, a shader unit (e.g., graphicsmultiprocessor 234 of FIG. 2C) may be configured to perform thefunctions of one or more of a vertex processing unit 504, a tessellationcontrol processing unit 508, a tessellation evaluation processing unit512, a geometry processing unit 516, and a fragment/pixel processingunit 524. The functions of data assembler 502, primitive assemblers 506,514, 518, tessellation unit 510, rasterizer 522, and raster operationsunit 526 may also be performed by other processing engines within aprocessing cluster (e.g., processing cluster 214 of FIG. 2A) and acorresponding partition unit (e.g., partition unit 220A-220N of FIG.2A). The graphics processing pipeline 500 may also be implemented usingdedicated processing units for one or more functions. In one embodiment,one or more portions of the graphics processing pipeline 500 can beperformed by parallel processing logic within a general purposeprocessor (e.g., CPU). In one embodiment, one or more portions of thegraphics processing pipeline 500 can access on-chip memory (e.g.,parallel processor memory 222 as in FIG. 2A) via a memory interface 528,which may be an instance of the memory interface 218 of FIG. 2A.

In one embodiment the data assembler 502 is a processing unit thatcollects vertex data for surfaces and primitives. The data assembler 502then outputs the vertex data, including the vertex attributes, to thevertex processing unit 504. The vertex processing unit 504 is aprogrammable execution unit that executes vertex shader programs,lighting and transforming vertex data as specified by the vertex shaderprograms. The vertex processing unit 504 reads data that is stored incache, local or system memory for use in processing the vertex data andmay be programmed to transform the vertex data from an object-basedcoordinate representation to a world space coordinate space or anormalized device coordinate space.

A first instance of a primitive assembler 506 receives vertex attributesfrom the vertex processing unit 504. The primitive assembler 506readings stored vertex attributes as needed and constructs graphicsprimitives for processing by tessellation control processing unit 508.The graphics primitives include triangles, line segments, points,patches, and so forth, as supported by various graphics processingapplication programming interfaces (APIs).

The tessellation control processing unit 508 treats the input verticesas control points for a geometric patch. The control points aretransformed from an input representation from the patch (e.g., thepatch's bases) to a representation that is suitable for use in surfaceevaluation by the tessellation evaluation processing unit 512. Thetessellation control processing unit 508 can also compute tessellationfactors for edges of geometric patches. A tessellation factor applies toa single edge and quantifies a view-dependent level of detail associatedwith the edge. A tessellation unit 510 is configured to receive thetessellation factors for edges of a patch and to tessellate the patchinto multiple geometric primitives such as line, triangle, orquadrilateral primitives, which are transmitted to a tessellationevaluation processing unit 512. The tessellation evaluation processingunit 512 operates on parameterized coordinates of the subdivided patchto generate a surface representation and vertex attributes for eachvertex associated with the geometric primitives.

A second instance of a primitive assembler 514 receives vertexattributes from the tessellation evaluation processing unit 512, readingstored vertex attributes as needed, and constructs graphics primitivesfor processing by the geometry processing unit 516. The geometryprocessing unit 516 is a programmable execution unit that executesgeometry shader programs to transform graphics primitives received fromprimitive assembler 514 as specified by the geometry shader programs. Inone embodiment the geometry processing unit 516 is programmed tosubdivide the graphics primitives into one or more new graphicsprimitives and calculate parameters used to rasterize the new graphicsprimitives.

In some embodiments the geometry processing unit 516 can add or deleteelements in the geometry stream. The geometry processing unit 516outputs the parameters and vertices specifying new graphics primitivesto primitive assembler 518. The primitive assembler 518 receives theparameters and vertices from the geometry processing unit 516 andconstructs graphics primitives for processing by a viewport scale, cull,and clip unit 520. The geometry processing unit 516 reads data that isstored in parallel processor memory or system memory for use inprocessing the geometry data. The viewport scale, cull, and clip unit520 performs clipping, culling, and viewport scaling and outputsprocessed graphics primitives to a rasterizer 522.

The rasterizer 522 can perform depth culling and other depth-basedoptimizations. The rasterizer 522 also performs scan conversion on thenew graphics primitives to generate fragments and output those fragmentsand associated coverage data to the fragment/pixel processing unit 524.The fragment/pixel processing unit 524 is a programmable execution unitthat is configured to execute fragment shader programs or pixel shaderprograms. The fragment/pixel processing unit 524 transforming fragmentsor pixels received from rasterizer 522, as specified by the fragment orpixel shader programs. For example, the fragment/pixel processing unit524 may be programmed to perform operations included but not limited totexture mapping, shading, blending, texture correction and perspectivecorrection to produce shaded fragments or pixels that are output to araster operations unit 526. The fragment/pixel processing unit 524 canread data that is stored in either the parallel processor memory or thesystem memory for use when processing the fragment data. Fragment orpixel shader programs may be configured to shade at sample, pixel, tile,or other granularities depending on the sampling rate configured for theprocessing units.

The raster operations unit 526 is a processing unit that performs rasteroperations including, but not limited to stencil, z test, blending, andthe like, and outputs pixel data as processed graphics data to be storedin graphics memory (e.g., parallel processor memory 222 as in FIG. 2A,and/or system memory 104 as in FIG. 1), to be displayed on the one ormore display device(s) 110 or for further processing by one of the oneor more processor(s) 102 or parallel processor(s) 112. In someembodiments the raster operations unit 526 is configured to compress zor color data that is written to memory and decompress z or color datathat is read from memory.

Low Precision Training of Deep Neural Networks

Deep Learning (DL) is one of the most predominant techniques driving theadoption of Machine Learning (ML) and Artificial Intelligence (AI)across a wide range of application domains. Deep learning can be appliedto applications including, but not limited to image recognition,autonomous driving, and natural language processing. DL applications aretrending towards leveraging lower precision representations to furtherincrease compute density, and such approximation lend themselvesnaturally to the inherent stochastic nature of the DL algorithms.

It has been established that Deep Learning inference can be performedusing eight or fewer bits, as inference tasks are known to tolerategreater noise due to the excess redundancy in the pre-trained models.However, training a deep neural network (DNN) at low precision is muchmore challenging due to increase sensitivity to variations in dynamicrange and precision. Specifically, computing weight gradients duringtraining requires higher dynamic range due to the large variations seenduring the backpropagation phase.

Half-precision floating point (FP16) has been touted as a solution forlow-precision DL training, with major manufacturers adding support forhalf-precision in their DL offerings. And yet, no one has been able todemonstrate end-to-end training using state-of-the-art networks usinglarge datasets such as ImageNet. It has been observed that the dynamicrange of the half-precision floating point is not enough forrepresenting the weight gradients and hence cannot be used for trainingDNNs such as convolutional neutral networks (CNNs) or recurrent neuralnetworks (RNNs).

Half-precision floating-point values have a dynamic range between6.10352×10⁻⁵ and 6.5540×10⁴, while a typical DNN has a data distributionthat is skewed more towards the smaller values, with weight gradientsthat are much smaller (e.g., in the order of 1.0×10⁻⁸). When weightgradients fall below the minimum half-precision value, a vanishinggradient problem can occur, which hampers the learning process. Whilethe gradients require much smaller values than half-precision floats,these gradients often do not use the higher end of the dynamic rangespectrum, particularly in deep neural networks employing normalization,where the data distribution is normalized to the range [0 . . . 1].

Scaling Half-Precision Floating Point Tensors for Training Deep NeuralNetworks

Embodiments described herein address the dynamic range limitations ofhalf-precision floating-point by enabling a scaled half-precisionfloating-point representation. In one embodiment, the scaledhalf-precision floating-point representation shifts the floating-pointvalues to a higher magnitude to utilize the full-range ofhalf-precision. In such embodiment, a specified bias is added to theexponent, which shifts the smaller gradients above the threshold thatcan be represented using half-precision floating-point values. In oneembodiment, hardware, software, and firmware logic is provided whichuses a bias value as a common scale factor to scale input tensors beforeconverting the tensors to half-precision floating-point. The scalingoperation addresses the dynamic range issue present duringhalf-precision training by pushing the training values to a highermagnitude, utilizing the unused range of half-precision encoding. Thescaling operation also preserves smaller gradients by shifting thegradients above the minimum threshold that can be represented using thehalf-precision floating-point format.

The bias value is computed based on the absolute maximum value of aninput tensor and the input dynamic range. In one embodiment the biasvalue is computed using a logic unit including a 32-bit floating-pointaccumulator. Where hardware logic is used to control the scaling andcompute operations, the hardware logic can perform the operations onhalf-precision FPUs having 32-bit accumulator logic. In embodiments inwhich the scaling and compute is directed in software or firmware, theinstructions used can explicitly specify the use of half-precisionoperations with 32-bit accumulation. The 32-bit intermediatefloating-point values can be scaled down to 16-bit floating point aftereach unit of compute using the scaled half-precision representationdescribed herein. For example, scaling can be performed after performingconvolution operations on a convolution layer of a convolutional neuralnetwork (CNN).

In one embodiment the exponent bias is dynamically adjusted based on thedynamic-range requirements at each neural network layer as the trainingprogresses. The core computation can be performed in the scaled domainand the results can be scaled back using exponent bias before thoseresults are passed to the next layer of the neural network or scaled tohalf-precision.

FIG. 6A illustrates a scaling operation 600 to avoid information lossduring 16-bit training, according to an embodiment. Embodimentsdescribed herein provide logic that creates a scaled FP16 tensor 602 foruse during neural network training. The typical distribution of deepneural network (DNN) gradient tensors 606 lies within the FP32 dynamicrange 607. However, converting the gradient tensors to FP16 may resultin significant information loss 604, particularly for gradients veryclose to zero. In one embodiment a scaled FP16 tensor 602 may be createdby scaling tensor data from the typical distribution of deep neuralnetwork (DNN) gradient tensors 606 into the FP16 dynamic range 605.After the scaling operation, the scaled FP16 tensor 602 has a scaledFP16 distribution 603 that allows training computations to be performedusing 16-bit floating point values without significant information loss604.

In one embodiment, scaled half-precision conversion is performed bymultiplying the input floating point tensor with 2^(BIAS), where BIAS isa per-tensor scale factor that is shared among values within the tensor.The scaling can be configured to push the values into a highermagnitude, utilizing the previously unused range of the half-precisionformat. In one embodiment, the BIAS is computed based on the absolutemaximum value of the input tensor and input dynamic range. Once the BIASis computed, the values within the input tensor, which are typically ofhigher precision, are then scaled and down-converted to a half-precisionFP16 format. In one embodiment, the scaled half-precision format is anIEEE 754 half-precision format. However, alternative formats may be usedfor internal representations, where those representations may betterrepresent the dynamic range of the training data. In one embodiment, oneor more non-IEEE half-precision formats may also be supported, asspecified by the instruction set architecture associated with thecompute units described herein.

The relationship between the original tensor and the scaled tensor canbe represented by the following formula:

ƒ_(s) ¹⁶=DownConvf₁₆(ƒ³²2^(BIAS))

The BIAS value is computed such that the final exponent of the scaledvalue is less than the largest exponent supported by half-precisionfloating point (<15). The scaling of input tensors prevents informationloss at the input to the layer. After the convolution or general matrixto matrix multiplication (GEMM) operation is performed at each layer,the dynamic range of the accumulated output values are changed andrescaled appropriately to ensure that the intermediate values do notbegin to exceed the upper bounds of the half-precision floating-pointformat used to store the values.

FIG. 6B illustrates logic 620 to perform a scaling operation, accordingto an embodiment. In one embodiment, the logic 620 includes hardwarelogic such as a compute unit 630, which can be any compute unit orexecution resource described herein. The compute logic 620 includes aninterconnect 631, which can be a fabric interconnect or one or morebusses that interconnect components within the compute unit 630. Theinterconnect 631 can connect input and output ports of the compute unit630 to a set of registers 633, functional units 640, and a range scalingunit 650. Input data, output data, and intermediate data for the computeunit 640 can be stored within the registers 633. The functional units640 can include, but are not limited to multipliers 642, adders 644,shifters 646, and load/store units 648. The multipliers 642 and adders644 can be configured to perform floating-point and/or integeroperations. The shifters 646 can be configured to perform bit-shiftoperations. The load/store units 648 can load data from memory and storethe data to a register in the set of registers 633, as well as storedata from the set of registers 633 to memory. The various functionalunits 640, in some embodiments, can be grouped into FPU or ALU units,which in turn can be grouped into GPGPU cores and/or load store units(e.g., GPGPU cores 262, Load/Store Unit 266 as in FIG. 2D).

The range scaling unit 650 can be configured to perform scalingoperations as described herein. In one embodiment the range scaling unit650 includes a bias unit 652, a scale unit 654, and a re-scale unit 656.The bias unit 652 can be configured to compute an exponent bias for ascaling operation. In one embodiment, the exponent bias is computedusing an absolute maximum (ABS_MAX) value of an input tensor and aninput dynamic range, as shown at block 704. The range scaling unit 650can additionally include a scale unit 654 and a re-scale unit 656. Thescale unit 654 can be configured to convert input weight and/oractivation data within input tensor data before performing computeoperations on the input tensor data via the functional units 640. There-scale unit 656 can then re-scale intermediate results before output.

FIG. 7A illustrates a flow diagram of logic 700 to perform scaledcompute operations on a layer of a deep neural network, according to anembodiment. In one embodiment the logic 700 can analyze the dynamicrange of input tensors at block 702 to determine whether to scale theinput tensors, as shown at block 703. The tensors are scaled if downconverting the tensors to a 16-bit format will result in informationloss, as illustrated in FIG. 6A. If the logic 700 will not scale theinput tensors at block 703, the logic can proceed to performing computeoperations such as multiply, add, or multiply-add operations, as shownat block 708. If the tensors are to be scaled, the logic 700 can computean exponent bias using the ABS_MAX value of the input tensor and theinput dynamic range, as shown at block 704. The logic 700 can thenconvert the weights and activations of the layer to scaled FP16 tensorsat block 706 before performing the compute operations at block 708. Oncethe compute operations are complete, the logic 700 can re-scale theweights and activations using the computed exponent bias anddown-convert to a scaled FP16 values at block 710 before processing thenext layer at block 712.

Dynamic Scaling Algorithm:

In a typical DNN layer, convolution operations accumulate inputs frommultiple input neurons resulting in longer accumulation chains. Usingthe scaled half-precision floats represents a risk of overflow orsaturation because the values are shifted towards larger magnitude,which can prevent the learning process from performing properly. Tocounter this issue, one embodiment includes logic to check the magnitudeof the output at regular intervals after a designated unit of compute.

FIG. 7B is a flow diagram illustrating logic 720 to implement a dynamicscaling algorithm, according to an embodiment. In one embodiment thelogic 720 is configured to check for saturation of the output and scalethe output values accordingly to prevent loss of data. In suchembodiment the logic 720 can analyze the dynamic range of input tensorsat block 722 to determine whether to scale the input tensors, as shownat block 723. If the input tensors are to be scaled, as determined atblock 723, the logic 720 can compute an exponent offset using theabsolute maximum value of the input tensor and the input dynamic range,as shown at block 732. The logic 720 can then convert the input tensorsto scaled FP16 tensors at block 734.

If scaling is not performed, as determined at block 723, or afterscaling has been performed at block 734, the logic 720 can perform thenecessary compute operations for the layer of the neural network atblock 724. The compute operations can include multiply, add, ormultiply-add operations, including multiply accumulate operations. Thecompute operations can be applied across multi-dimensional input tensorsin response to a single instruction. The logic 720 can then check if theintermediate results are close to saturation at block 726. If theintermediate results are close to saturation at block 727, the logic 720can re-scale the outputs and update the exponent bias value at block 728before performing additional compute operations at block 724. Otherwise,the logic 720 can continue the compute operations at block 724 withoutre-scaling.

FIG. 7C is a block diagram of a data processing system 730, according toan embodiment. The data processing system 730 is a heterogeneousprocessing system having a processor 732, unified memory 740, and aGPGPU 750 including machine learning acceleration logic. The processor732 and the GPGPU 750 can be any of the processors and GPGPU/parallelprocessors as described herein. The processor 732 can executeinstructions for a compiler 745 stored in system memory 742. Thecompiler 745 executes on the processor 732 to compile source code 744Ainto compiled code 744B. The compiled code 744B can include code thatmay be executed by the processor 732 and/or code that may be executed bythe GPGPU 750. During compilation, the compiler 745 can performoperations to insert metadata, including hints as to the level of dataparallelism present in the compiled code 744B and/or hints regarding thedata locality associated with threads to be dispatched based on thecompiled code 744B. The compiler 745 can include the informationnecessary to perform such operations or the operations can be performedwith the assistance of a runtime library 746. The runtime library 746can also facilitate the compiler 745 in the compilation of the sourcecode 744A and can also include instructions that are linked at runtimewith the compiled code 744B to facilitate execution of the compiledinstructions on the GPGPU 750.

The unified memory 740 represents a unified address space that may beaccessed by the processor 732 and the GPGPU 750. The unified memoryincludes system memory 742 as well as GPGPU memory 748. The GPGPU memory748 includes GPGPU local memory 728 within the GPGPU 750 and can alsoinclude some or all of system memory 742. example, compiled code 744Bstored in system memory 742 can also be mapped into GPGPU memory 748 foraccess by the GPGPU 750.

The GPGPU 750 includes multiple compute blocks 754A-754N, which can beinstances of the compute clusters 214A-214N of FIG. 2A, or the exemplaryprocessing cluster 214 of FIG. 2C. Each of the multiple compute block754A-754N can include multiple compute units, which can be a group ofcores, multiprocessors, execution units, or other execution resourcesdescribed herein, that can execute multiple threads within a threadgroup. For example, and in one embodiment the compute blocks 754A-754Ncan each include a set of graphics multiprocessors, each of which can bea graphics multiprocessor 234 as in FIG. 2C. The graphics multiprocessor234 can include multiple GPGPU cores, such as the GPGPU cores 262 as inFIG. 2D. Each graphics multiprocessor can execute parallel threads of aninstruction stream. The multiprocessor can include an instruction unitfor processing incoming instructions of an instruction stream, as wellas a scheduler to schedule instructions to the various GPGPU cores.

The GPGPU 750 also includes a set of registers 755, cache memory 727,and a power and performance module 756 that can be used as sharedresources for the compute blocks 754A-754N. The power and performancemodule 756 can be configured to adjust power delivery and clockfrequencies for the compute blocks 754A-754N to power gate idlecomponents within the compute blocks 754A-754N under heavy workloads.The GPGPU 750 includes GPGPU local memory 728, which is physical memorythat shares a graphics card or multi-chip module with the GPGPU 750.

In one embodiment, the GPGPU 750 includes compute logic optimized toaccelerate machine learning operations. The compute logic includes aninstruction unit 751, a scheduler unit 752, and a range scaling module753. The instruction unit 751 includes logic to fetch, decode, andpre-process instructions that define complex compute pipeline behavior.The complex pipeline behavior specified by an instruction can besequenced and/or serialized via the scheduler unit 752, which canschedule multiple operations per instructions to a compute block754A-754N that includes multiple clustered parallel processor units. Inone embodiment, the range scaling module 753 includes logic to performscaled compute operations on a layer of a deep neural network. The rangescaling module 753 can work in conjunction with the instruction unit751, scheduler unit 752, and compute blocks 754A-754N to enableexecution of range scaling instructions. In one embodiment, the rangescaling module 753 can configure hardware logic within compute units ofthe GPGPU 750 to implement the logic 700, 720 as in FIG. 7A-7B. Forexample, the range scaling module 753 can provide instructions orcontrols to enable a range scaling unit (e.g., range scaling unit 650 asin FIG. 6B) within compute units of the compute block 754A-754N to scalethe dynamic range of input tensors before and after performingoperations on the input tensors. In one embodiment, the range scalingmodule 753 is implemented at least in part using one or more shaderprograms that execute within the compute blocks 754A-754N.

Machine Learning Overview

A machine learning algorithm is an algorithm that can learn based on aset of data. Embodiments of machine learning algorithms can be designedto model high-level abstractions within a data set. For example, imagerecognition algorithms can be used to determine which of severalcategories to which a given input belong; regression algorithms canoutput a numerical value given an input; and pattern recognitionalgorithms can be used to generate translated text or perform text tospeech and/or speech recognition.

An exemplary type of machine learning algorithm is a neural network.There are many types of neural networks; a simple type of neural networkis a feedforward network. A feedforward network may be implemented as anacyclic graph in which the nodes are arranged in layers. Typically, afeedforward network topology includes an input layer and an output layerthat are separated by at least one hidden layer. The hidden layertransforms input received by the input layer into a representation thatis useful for generating output in the output layer. The network nodesare fully connected via edges to the nodes in adjacent layers, but thereare no edges between nodes within each layer. Data received at the nodesof an input layer of a feedforward network are propagated (i.e., “fedforward”) to the nodes of the output layer via an activation functionthat calculates the states of the nodes of each successive layer in thenetwork based on coefficients (“weights”) respectively associated witheach of the edges connecting the layers. Depending on the specific modelbeing represented by the algorithm being executed, the output from theneural network algorithm can take various forms.

Before a machine learning algorithm can be used to model a particularproblem, the algorithm is trained using a training data set. Training aneural network involves selecting a network topology, using a set oftraining data representing a problem being modeled by the network, andadjusting the weights until the network model performs with a minimalerror for all instances of the training data set. For example, during asupervised learning training process for a neural network, the outputproduced by the network in response to the input representing aninstance in a training data set is compared to the “correct” labeledoutput for that instance, an error signal representing the differencebetween the output and the labeled output is calculated, and the weightsassociated with the connections are adjusted to minimize that error asthe error signal is backward propagated through the layers of thenetwork. The network is considered “trained” when the errors for each ofthe outputs generated from the instances of the training data set areminimized.

The accuracy of a machine learning algorithm can be affectedsignificantly by the quality of the data set used to train thealgorithm. The training process can be computationally intensive and mayrequire a significant amount of time on a conventional general-purposeprocessor. Accordingly, parallel processing hardware is used to trainmany types of machine learning algorithms. This is particularly usefulfor optimizing the training of neural networks, as the computationsperformed in adjusting the coefficients in neural networks lendthemselves naturally to parallel implementations. Specifically, manymachine learning algorithms and software applications have been adaptedto make use of the parallel processing hardware within general-purposegraphics processing devices.

FIG. 8 is a generalized diagram of a machine learning software stack800. A machine learning application 802 can be configured to train aneural network using a training dataset or to use a trained deep neuralnetwork to implement machine intelligence. The machine learningapplication 802 can include training and inference functionality for aneural network and/or specialized software that can be used to train aneural network before deployment. The machine learning application 802can implement any type of machine intelligence including but not limitedto image recognition, mapping and localization, autonomous navigation,speech synthesis, medical imaging, or language translation.

Hardware acceleration for the machine learning application 802 can beenabled via a machine learning framework 804. The machine learningframework 804 can provide a library of machine learning primitives.Machine learning primitives are basic operations that are commonlyperformed by machine learning algorithms. Without the machine learningframework 804, developers of machine learning algorithms would berequired to create and optimize the main computational logic associatedwith the machine learning algorithm, then re-optimize the computationallogic as new parallel processors are developed. Instead, the machinelearning application can be configured to perform the necessarycomputations using the primitives provided by the machine learningframework 804. Exemplary primitives include tensor convolutions,activation functions, and pooling, which are computational operationsthat are performed while training a convolutional neural network (CNN).The machine learning framework 804 can also provide primitives toimplement basic linear algebra subprograms performed by manymachine-learning algorithms, such as matrix and vector operations.

The machine learning framework 804 can process input data received fromthe machine learning application 802 and generate the appropriate inputto a compute framework 806. The compute framework 806 can abstract theunderlying instructions provided to the GPGPU driver 808 to enable themachine learning framework 804 to take advantage of hardwareacceleration via the GPGPU hardware 810 without requiring the machinelearning framework 804 to have intimate knowledge of the architecture ofthe GPGPU hardware 810. Additionally, the compute framework 806 canenable hardware acceleration for the machine learning framework 804across a variety of types and generations of the GPGPU hardware 810.

GPGPU Machine Learning Acceleration

FIG. 9 illustrates a highly-parallel general-purpose graphics processingunit 900, according to an embodiment. In one embodiment thegeneral-purpose processing unit (GPGPU) 900 can be configured to beparticularly efficient in processing the type of computational workloadsassociated with training deep neural networks. Additionally, the GPGPU900 can be linked directly to other instances of the GPGPU to create amulti-GPU cluster to improve training speed for particularly deep neuralnetworks.

The GPGPU 900 includes a host interface 902 to enable a connection witha host processor. In one embodiment the host interface 902 is a PCIExpress interface. However, the host interface can also be a vendorspecific communications interface or communications fabric. The GPGPU900 receives commands from the host processor and uses a globalscheduler 904 to distribute execution threads associated with thosecommands to a set of compute clusters 906A-906H. The compute clusters906A-906H share a cache memory 908. The cache memory 908 can serve as ahigher-level cache for cache memories within the compute clusters906A-906H.

The GPGPU 900 includes memory 914A-914B coupled with the computeclusters 906A-906H via a set of memory controllers 912A-912B. In variousembodiments, the memory 914A-914B can include various types of memorydevices including dynamic random access memory (DRAM) or graphics randomaccess memory, such as synchronous graphics random access memory(SGRAM), including graphics double data rate (GDDR) memory or 3D stackedmemory, including but not limited to high bandwidth memory (e.g., HBM,HBM2)

In one embodiment each compute cluster 906A-906H includes a set ofgraphics multiprocessors, such as the graphics multiprocessor 400 ofFIG. 4A. The graphics multiprocessors of the compute cluster multipletypes of integer and floating-point logic units that can performcomputational operations at a range of precisions including suited formachine learning computations. For example, and in one embodiment atleast a subset of the floating point units in each of the computeclusters 906A-906H can be configured to perform 16-bit or 32-bitfloating point operations, while a different subset of the floatingpoint units can be configured to perform 64-bit floating pointoperations.

Multiple instances of the GPGPU 900 can be configured to operate as acompute cluster. The communication mechanism used by the compute clusterfor synchronization and data exchange varies across embodiments. In oneembodiment the multiple instances of the GPGPU 900 communicate over thehost interface 902. In one embodiment the GPGPU 900 includes an I/O hub909 that couples the GPGPU 900 with a GPU link 910 that enables a directconnection to other instances of the GPGPU. In one embodiment the GPUlink 910 is coupled to a dedicated GPU-to-GPU bridge that enablescommunication and synchronization between multiple instances of theGPGPU 900. In one embodiment the GPU link 910 couples with a high speedinterconnect to transmit and receive data to other GPGPUs or parallelprocessors. In one embodiment the multiple instances of the GPGPU 900are located in separate data processing systems and communicate via anetwork device that is accessible via the host interface 902. In oneembodiment the GPU link 910 can be configured to enable a connection toa host processor in addition to or as an alternative to the hostinterface 902.

While the illustrated configuration of the GPGPU 900 can be configuredto train neural networks, one embodiment provides alternateconfiguration of the GPGPU 900 that can be configured for deploymentwithin a high performance or low power inferencing platform. In aninferencing configuration the GPGPU 900 includes fewer of the computeclusters 906A-H relative to the training configuration. Additionallymemory technology associated with the memory 914A-914B may differbetween inferencing and training configurations. In one embodiment theinferencing configuration of the GPGPU 900 can support inferencingspecific instructions. For example, an inferencing configuration canprovide support for one or more 8-bit integer dot product instructions,which are commonly used during inferencing operations for deployedneural networks.

FIG. 10 illustrates a multi-GPU computing system 1000, according to anembodiment. The multi-GPU computing system 1000 can include a processor1002 coupled to multiple GPGPUs 1006A-1006D via a host interface switch1004. The host interface switch 1004, in one embodiment, is a PCIexpress switch device that couples the processor 1002 to a PCI expressbus over which the processor 1002 can communicate with the set of GPGPUs1006A-1006D. Each of the multiple GPGPUs 1006A-1006D can be an instanceof the GPGPU 900 of FIG. 9. The GPGPUs 1006A-D can interconnect via aset of high-speed point to point GPU to GPU links 1016. The high-speedGPU to GPU links can connect to each of the GPGPUs 1006A-D via adedicated GPU link, such as the GPU link 910 as in FIG. 9. The P2P GPUlinks 1016 enable direct communication between each of the GPGPUs1006A-1006D without requiring communication over the host interface busto which the processor 1002 is connected. With GPU-to-GPU trafficdirected to the P2P GPU links, the host interface bus remains availablefor system memory access or to communicate with other instances of themulti-GPU computing system 1000, for example, via one or more networkdevices. While in the illustrated embodiment the GPGPUs 1006A-1006Dconnect to the processor 1002 via the host interface switch 1004, in oneembodiment the processor 1002 includes direct support for the P2P GPUlinks 1016 and can connect directly to the GPGPUs 1006A-1006D.

Machine Learning Neural Network Implementations

The computing architecture provided by embodiments described herein canbe configured to perform the types of parallel processing that isparticularly suited for training and deploying neural networks formachine learning. A neural network can be generalized as a network offunctions having a graph relationship. As is well-known in the art,there are a variety of types of neural network implementations used inmachine learning. One exemplary type of neural network is thefeedforward network, as previously described.

A second exemplary type of neural network is the Convolutional NeuralNetwork (CNN). A CNN is a specialized feedforward neural network forprocessing data having a known, grid-like topology, such as image data.Accordingly, CNNs are commonly used for compute vision and imagerecognition applications, but they also may be used for other types ofpattern recognition such as speech and language processing. The nodes inthe CNN input layer are organized into a set of “filters” (featuredetectors inspired by the receptive fields found in the retina), and theoutput of each set of filters is propagated to nodes in successivelayers of the network. The computations for a CNN include applying theconvolution mathematical operation to each filter to produce the outputof that filter. Convolution is a specialized kind of mathematicaloperation performed by two functions to produce a third function that isa modified version of one of the two original functions. Inconvolutional network terminology, the first function to the convolutioncan be referred to as the input, while the second function can bereferred to as the convolution kernel. The output may be referred to asthe feature map. For example, the input to a convolution layer can be amultidimensional array of data that defines the various color componentsof an input image. The convolution kernel can be a multidimensionalarray of parameters, where the parameters are adapted by the trainingprocess for the neural network.

Recurrent neural networks (RNNs) are a family of feedforward neuralnetworks that include feedback connections between layers. RNNs enablemodeling of sequential data by sharing parameter data across differentparts of the neural network. The architecture for an RNN includescycles. The cycles represent the influence of a present value of avariable on its own value at a future time, as at least a portion of theoutput data from the RNN is used as feedback for processing subsequentinput in a sequence. This feature makes RNNs particularly useful forlanguage processing due to the variable nature in which language datacan be composed.

The figures described below present exemplary feedforward, CNN, and RNNnetworks, as well as describe a general process for respectivelytraining and deploying each of those types of networks. It will beunderstood that these descriptions are exemplary and non-limiting as toany specific embodiment described herein and the concepts illustratedcan be applied generally to deep neural networks and machine learningtechniques in general.

The exemplary neural networks described above can be used to performdeep learning. Deep learning is machine learning using deep neuralnetworks. The deep neural networks used in deep learning are artificialneural networks composed of multiple hidden layers, as opposed toshallow neural networks that include only a single hidden layer. Deeperneural networks are generally more computationally intensive to train.However, the additional hidden layers of the network enable multisteppattern recognition that results in reduced output error relative toshallow machine learning techniques.

Deep neural networks used in deep learning typically include a front-endnetwork to perform feature recognition coupled to a back-end networkwhich represents a mathematical model that can perform operations (e.g.,object classification, speech recognition, etc.) based on the featurerepresentation provided to the model. Deep learning enables machinelearning to be performed without requiring hand crafted featureengineering to be performed for the model. Instead, deep neural networkscan learn features based on statistical structure or correlation withinthe input data. The learned features can be provided to a mathematicalmodel that can map detected features to an output. The mathematicalmodel used by the network is generally specialized for the specific taskto be performed, and different models will be used to perform differenttask.

Once the neural network is structured, a learning model can be appliedto the network to train the network to perform specific tasks. Thelearning model describes how to adjust the weights within the model toreduce the output error of the network. Backpropagation of errors is acommon method used to train neural networks. An input vector ispresented to the network for processing. The output of the network iscompared to the desired output using a loss function and an error valueis calculated for each of the neurons in the output layer. The errorvalues are then propagated backwards until each neuron has an associatederror value which roughly represents its contribution to the originaloutput. The network can then learn from those errors using an algorithm,such as the stochastic gradient descent algorithm, to update the weightsof the of the neural network.

FIG. 11A-B illustrate an exemplary convolutional neural network. FIG.11A illustrates various layers within a CNN. As shown in FIG. 11A, anexemplary CNN used to model image processing can receive input 1102describing the red, green, and blue (RGB) components of an input image.The input 1102 can be processed by multiple convolutional layers (e.g.,convolutional layer 1104, convolutional layer 1106). The output from themultiple convolutional layers may optionally be processed by a set offully connected layers 1108. Neurons in a fully connected layer havefull connections to all activations in the previous layer, as previouslydescribed for a feedforward network. The output from the fully connectedlayers 1108 can be used to generate an output result from the network.The activations within the fully connected layers 1108 can be computedusing matrix multiplication instead of convolution. Not all CNNimplementations are configured to make use of fully connected layers1108. For example, in some implementations the convolutional layer 1106can generate output for the CNN.

The convolutional layers are sparsely connected, which differs fromtraditional neural network configuration found in the fully connectedlayers 1108. Traditional neural network layers are fully connected, suchthat every output unit interacts with every input unit. However, theconvolutional layers are sparsely connected because the output of theconvolution of a field is input (instead of the respective state valueof each of the nodes in the field) to the nodes of the subsequent layer,as illustrated. The kernels associated with the convolutional layersperform convolution operations, the output of which is sent to the nextlayer. The dimensionality reduction performed within the convolutionallayers is one aspect that enables the CNN to scale to process largeimages.

FIG. 11B illustrates exemplary computation stages within a convolutionallayer of a CNN. Input to a convolutional layer 1112 of a CNN can beprocessed in three stages of a convolutional layer 1114. The threestages can include a convolution stage 1116, a detector stage 1118, anda pooling stage 1120. The convolutional layer 1114 can then output datato a successive convolutional layer. The final convolutional layer ofthe network can generate output feature map data or provide input to afully connected layer, for example, to generate a classification valuefor the input to the CNN.

In the convolution stage 1116 performs several convolutions in parallelto produce a set of linear activations. The convolution stage 1116 caninclude an affine transformation, which is any transformation that canbe specified as a linear transformation plus a translation. Affinetransformations include rotations, translations, scaling, andcombinations of these transformations. The convolution stage computesthe output of functions (e.g., neurons) that are connected to specificregions in the input, which can be determined as the local regionassociated with the neuron. The neurons compute a dot product betweenthe weights of the neurons and the region in the local input to whichthe neurons are connected. The output from the convolution stage 1116defines a set of linear activations that are processed by successivestages of the convolutional layer 1114.

The linear activations can be processed by a detector stage 1118. In thedetector stage 1118, each linear activation is processed by a non-linearactivation function. The non-linear activation function increases thenonlinear properties of the overall network without affecting thereceptive fields of the convolution layer. Several types of non-linearactivation functions may be used. One particular type is the rectifiedlinear unit (ReLU), which uses an activation function defined asƒ(x)=max(0,x), such that the activation is thresholded at zero.

The pooling stage 1120 uses a pooling function that replaces the outputof the convolutional layer 1106 with a summary statistic of the nearbyoutputs. The pooling function can be used to introduce translationinvariance into the neural network, such that small translations to theinput do not change the pooled outputs. Invariance to local translationcan be useful in scenarios where the presence of a feature in the inputdata is more important than the precise location of the feature. Varioustypes of pooling functions can be used during the pooling stage 1120,including max pooling, average pooling, and l2-norm pooling.Additionally, some CNN implementations do not include a pooling stage.Instead, such implementations substitute and additional convolutionstage having an increased stride relative to previous convolutionstages.

The output from the convolutional layer 1114 can then be processed bythe next layer 1122. The next layer 1122 can be an additionalconvolutional layer or one of the fully connected layers 1108. Forexample, the first convolutional layer 1104 of FIG. 11A can output tothe second convolutional layer 1106, while the second convolutionallayer can output to a first layer of the fully connected layers 1108.

FIG. 12 illustrates an exemplary recurrent neural network 1200. In arecurrent neural network (RNN), the previous state of the networkinfluences the output of the current state of the network. RNNs can bebuilt in a variety of ways using a variety of functions. The use of RNNsgenerally revolves around using mathematical models to predict thefuture based on a prior sequence of inputs. For example, an RNN may beused to perform statistical language modeling to predict an upcomingword given a previous sequence of words. The illustrated RNN 1200 can bedescribed has having an input layer 1202 that receives an input vector,hidden layers 1204 to implement a recurrent function, a feedbackmechanism 1205 to enable a ‘memory’ of previous states, and an outputlayer 1206 to output a result. The RNN 1200 operates based ontime-steps. The state of the RNN at a given time step is influencedbased on the previous time step via the feedback mechanism 1205. For agiven time step, the state of the hidden layers 1204 is defined by theprevious state and the input at the current time step. An initial input(x₁) at a first time step can be processed by the hidden layer 1204. Asecond input (x₂) can be processed by the hidden layer 1204 using stateinformation that is determined during the processing of the initialinput (x₁). A given state can be computed as s_(t)=ƒ(Ux_(t)+Ws_(t−1)),where U and W are parameter matrices. The function ƒ is generally anonlinearity, such as the hyperbolic tangent function (Tanh) or avariant of the rectifier function ƒ(x)=max(0,x). However, the specificmathematical function used in the hidden layers 1204 can vary dependingon the specific implementation details of the RNN 1200.

In addition to the basic CNN and RNN networks described, variations onthose networks may be enabled. One example RNN variant is the long shortterm memory (LSTM) RNN. LSTM RNNs are capable of learning long-termdependencies that may be necessary for processing longer sequences oflanguage. A variant on the CNN is a convolutional deep belief network,which has a structure similar to a CNN and is trained in a mannersimilar to a deep belief network. A deep belief network (DBN) is agenerative neural network that is composed of multiple layers ofstochastic (random) variables. DBNs can be trained layer-by-layer usinggreedy unsupervised learning. The learned weights of the DBN can then beused to provide pre-train neural networks by determining an optimalinitial set of weights for the neural network.

FIG. 13 illustrates training and deployment of a deep neural network.Once a given network has been structured for a task the neural networkis trained using a training dataset 1302. Various training frameworkshave been developed to enable hardware acceleration of the trainingprocess. For example, the machine learning framework 804 of FIG. 8 maybe configured as a training framework 1304. The training framework 1304can hook into an untrained neural network 1306 and enable the untrainedneural net to be trained using the parallel processing resourcesdescribed herein to generate a trained neural network 1308.

To start the training process the initial weights may be chosen randomlyor by pre-training using a deep belief network. The training cycle thenbe performed in either a supervised or unsupervised manner.

Supervised learning is a learning method in which training is performedas a mediated operation, such as when the training dataset 1302 includesinput paired with the desired output for the input, or where thetraining dataset includes input having known output and the output ofthe neural network is manually graded. The network processes the inputsand compares the resulting outputs against a set of expected or desiredoutputs. Errors are then propagated back through the system. Thetraining framework 1304 can adjust to adjust the weights that controlthe untrained neural network 1306. The training framework 1304 canprovide tools to monitor how well the untrained neural network 1306 isconverging towards a model suitable to generating correct answers basedon known input data. The training process occurs repeatedly as theweights of the network are adjusted to refine the output generated bythe neural network. The training process can continue until the neuralnetwork reaches a statistically desired accuracy associated with atrained neural network 1308. The trained neural network 1308 can then bedeployed to implement any number of machine learning operations togenerate an inference result 1314 based on input of new data 1312.

Unsupervised learning is a learning method in which the network attemptsto train itself using unlabeled data. Thus, for unsupervised learningthe training dataset 1302 will include input data without any associatedoutput data. The untrained neural network 1306 can learn groupingswithin the unlabeled input and can determine how individual inputs arerelated to the overall dataset. Unsupervised training can be used togenerate a self-organizing map, which is a type of trained neuralnetwork 1308 capable of performing operations useful in reducing thedimensionality of data. Unsupervised training can also be used toperform anomaly detection, which allows the identification of datapoints in an input dataset that deviate from the normal patterns of thedata.

Variations on supervised and unsupervised training may also be employed.Semi-supervised learning is a technique in which in the training dataset1302 includes a mix of labeled and unlabeled data of the samedistribution. Incremental learning is a variant of supervised learningin which input data is continuously used to further train the model.Incremental learning enables the trained neural network 1308 to adapt tothe new data 1312 without forgetting the knowledge instilled within thenetwork during initial training.

Whether supervised or unsupervised, the training process forparticularly deep neural networks may be too computationally intensivefor a single compute node. Instead of using a single compute node, adistributed network of computational nodes can be used to accelerate thetraining process.

FIG. 14 is a block diagram illustrating distributed learning.Distributed learning is a training model that uses multiple distributedcomputing nodes to perform supervised or unsupervised training of aneural network. The distributed computational nodes can each include oneor more host processors and one or more of the general-purposeprocessing nodes, such as the highly-parallel general-purpose graphicsprocessing unit 900 as in FIG. 9. As illustrated, distributed learningcan be performed model parallelism 1402, data parallelism 1404, or acombination of model and data parallelism 1404.

In model parallelism 1402, different computational nodes in adistributed system can perform training computations for different partsof a single network. For example, each layer of a neural network can betrained by a different processing node of the distributed system. Thebenefits of model parallelism include the ability to scale toparticularly large models. Splitting the computations associated withdifferent layers of the neural network enables the training of verylarge neural networks in which the weights of all layers would not fitinto the memory of a single computational node. In some instances, modelparallelism can be particularly useful in performing unsupervisedtraining of large neural networks.

In data parallelism 1404, the different nodes of the distributed networkhave a complete instance of the model and each node receives a differentportion of the data. The results from the different nodes are thencombined. While different approaches to data parallelism are possible,data parallel training approaches all require a technique of combiningresults and synchronizing the model parameters between each node.Exemplary approaches to combining data include parameter averaging andupdate based data parallelism. Parameter averaging trains each node on asubset of the training data and sets the global parameters (e.g.,weights, biases) to the average of the parameters from each node.Parameter averaging uses a central parameter server that maintains theparameter data. Update based data parallelism is similar to parameteraveraging except that instead of transferring parameters from the nodesto the parameter server, the updates to the model are transferred.Additionally, update based data parallelism can be performed in adecentralized manner, where the updates are compressed and transferredbetween nodes.

A hybrid parallelism technique of combined model and data parallelism1406 can be implemented, for example, in a distributed system in whicheach computational node includes multiple GPUs. Each node can have acomplete instance of the model with separate GPUs within each node areused to train different portions of the model.

Distributed training has increased overhead relative to training on asingle machine. However, the parallel processors and GPGPUs describedherein can each implement various techniques to reduce the overhead ofdistributed training, including techniques to enable high bandwidthGPU-to-GPU data transfer and accelerated remote data synchronization.

Exemplary Machine Learning Applications

Machine learning can be applied to solve a variety of technologicalproblems, including but not limited to computer vision, autonomousdriving and navigation, speech recognition, and language processing.Computer vision has traditionally been one of the most active researchareas for machine learning applications. Applications of computer visionrange from reproducing human visual abilities, such as recognizingfaces, to creating new categories of visual abilities. For example,computer vision applications can be configured to recognize sound wavesfrom the vibrations induced in objects visible in a video. Parallelprocessor accelerated machine learning enables computer visionapplications to be trained using significantly larger training datasetthan previously feasible and enables inferencing systems to be deployedusing low power parallel processors.

Parallel processor accelerated machine learning has autonomous drivingapplications including lane and road sign recognition, obstacleavoidance, navigation, and driving control. Accelerated machine learningtechniques can be used to train driving models based on datasets thatdefine the appropriate responses to specific training input. Theparallel processors described herein can enable rapid training of theincreasingly complex neural networks used for autonomous drivingsolutions and enables the deployment of low power inferencing processorsin a mobile platform suitable for integration into autonomous vehicles.

Parallel processor accelerated deep neural networks have enabled machinelearning approaches to automatic speech recognition (ASR). ASR includesthe creation of a function that computes the most probable linguisticsequence given an input acoustic sequence. Accelerated machine learningusing deep neural networks have enabled the replacement of the hiddenMarkov models (HMMs) and Gaussian mixture models (GMMs) previously usedfor ASR.

Parallel processor accelerated machine learning can also be used toaccelerate natural language processing. Automatic learning procedurescan make use of statistical inference algorithms to produce models thatare robust to erroneous or unfamiliar input. Exemplary natural languageprocessor applications include automatic machine translation betweenhuman languages.

The parallel processing platforms used for machine learning can bedivided into training platforms and deployment platforms. Trainingplatforms are generally highly parallel and include optimizations toaccelerate multi-GPU single node training and multi-node, multi-GPUtraining. Exemplary parallel processors suited for training include thehighly-parallel general-purpose graphics processing unit 900 of FIG. 9and the multi-GPU computing system 1000 of FIG. 10. On the contrary,deployed machine learning platforms generally include lower powerparallel processors suitable for use in products such as cameras,autonomous robots, and autonomous vehicles.

FIG. 15 illustrates an exemplary inferencing system on a chip (SOC) 1500suitable for performing inferencing using a trained model. The SOC 1500can integrate processing components including a media processor 1502, avision processor 1504, a GPGPU 1506 and a multi-core processor 1508. TheSOC 1500 can additionally include an on-chip memory 1505 that can enablea shared on-chip data pool that is accessible by each of the processingcomponents. The processing components can be optimized for low poweroperation to enable deployment to a variety of machine learningplatforms, including autonomous vehicles and autonomous robots. Forexample, one implementation of the SOC 1500 can be used as a portion ofthe main control system for an autonomous vehicle. Where the SOC 1500 isconfigured for use in autonomous vehicles the SOC is designed andconfigured for compliance with the relevant functional safety standardsof the deployment jurisdiction.

During operation, the media processor 1502 and vision processor 1504 canwork in concert to accelerate computer vision operations. The mediaprocessor 1502 can enable low latency decode of multiple high-resolution(e.g., 4K, 8K) video streams. The decoded video streams can be writtento a buffer in the on-chip memory 1505. The vision processor 1504 canthen parse the decoded video and perform preliminary processingoperations on the frames of the decoded video in preparation ofprocessing the frames using a trained image recognition model. Forexample, the vision processor 1504 can accelerate convolution operationsfor a CNN that is used to perform image recognition on thehigh-resolution video data, while back end model computations areperformed by the GPGPU 1506.

The multi-core processor 1508 can include control logic to assist withsequencing and synchronization of data transfers and shared memoryoperations performed by the media processor 1502 and the visionprocessor 1504. The multi-core processor 1508 can also function as anapplication processor to execute software applications that can make useof the inferencing compute capability of the GPGPU 1506. For example, atleast a portion of the navigation and driving logic can be implementedin software executing on the multi-core processor 1508. Such softwarecan directly issue computational workloads to the GPGPU 1506 or thecomputational workloads can be issued to the multi-core processor 1508,which can offload at least a portion of those operations to the GPGPU1506.

The GPGPU 1506 can include compute clusters such as a low powerconfiguration of the compute clusters 906A-906H within thehighly-parallel general-purpose graphics processing unit 900. Thecompute clusters within the GPGPU 1506 can support instruction that arespecifically optimized to perform inferencing computations on a trainedneural network. For example, the GPGPU 1506 can support instructions toperform low precision computations such as 8-bit and 4-bit integervector operations.

Additional Exemplary Graphics Processing System

Details of the embodiments described above can be incorporated withingraphics processing systems and devices described below. The graphicsprocessing system and devices described below illustrate alternativesystems and graphics processing hardware that can implement any and allof the techniques described above.

Additional Exemplary Graphics Processing System Overview

FIG. 16 is a block diagram of a processing system 1600, according to anembodiment. In various embodiments the system 1600 includes one or moreprocessors 1602 and one or more graphics processors 1608, and may be asingle processor desktop system, a multiprocessor workstation system, ora server system having a large number of processors 1602 or processorcores 1607. In one embodiment, the system 1600 is a processing platformincorporated within a system-on-a-chip (SoC) integrated circuit for usein mobile, handheld, or embedded devices.

An embodiment of system 1600 can include, or be incorporated within aserver-based gaming platform, a game console, including a game and mediaconsole, a mobile gaming console, a handheld game console, or an onlinegame console. In some embodiments system 1600 is a mobile phone, smartphone, tablet computing device or mobile Internet device. Dataprocessing system 1600 can also include, couple with, or be integratedwithin a wearable device, such as a smart watch wearable device, smarteyewear device, augmented reality device, or virtual reality device. Insome embodiments, data processing system 1600 is a television or set topbox device having one or more processors 1602 and a graphical interfacegenerated by one or more graphics processors 1608.

In some embodiments, the one or more processors 1602 each include one ormore processor cores 1607 to process instructions which, when executed,perform operations for system and user software. In some embodiments,each of the one or more processor cores 1607 is configured to process aspecific instruction set 1609. In some embodiments, instruction set 1609may facilitate Complex Instruction Set Computing (CISC), ReducedInstruction Set Computing (RISC), or computing via a Very LongInstruction Word (VLIW). Multiple processor cores 1607 may each processa different instruction set 1609, which may include instructions tofacilitate the emulation of other instruction sets. Processor core 1607may also include other processing devices, such a Digital SignalProcessor (DSP).

In some embodiments, the processor 1602 includes cache memory 1604.Depending on the architecture, the processor 1602 can have a singleinternal cache or multiple levels of internal cache. In someembodiments, the cache memory is shared among various components of theprocessor 1602. In some embodiments, the processor 1602 also uses anexternal cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC))(not shown), which may be shared among processor cores 1607 using knowncache coherency techniques. A register file 1606 is additionallyincluded in processor 1602 which may include different types ofregisters for storing different types of data (e.g., integer registers,floating point registers, status registers, and an instruction pointerregister). Some registers may be general-purpose registers, while otherregisters may be specific to the design of the processor 1602.

In some embodiments, processor 1602 is coupled with a processor bus 1610to transmit communication signals such as address, data, or controlsignals between processor 1602 and other components in system 1600. Inone embodiment the system 1600 uses an exemplary ‘hub’ systemarchitecture, including a memory controller hub 1616 and an Input Output(I/O) controller hub 1630. A memory controller hub 1616 facilitatescommunication between a memory device and other components of system1600, while an I/O Controller Hub (ICH) 1630 provides connections to I/Odevices via a local I/O bus. In one embodiment, the logic of the memorycontroller hub 1616 is integrated within the processor.

Memory device 1620 can be a dynamic random access memory (DRAM) device,a static random access memory (SRAM) device, flash memory device,phase-change memory device, or some other memory device having suitableperformance to serve as process memory. In one embodiment the memorydevice 1620 can operate as system memory for the system 1600, to storedata 1622 and instructions 1621 for use when the one or more processors1602 executes an application or process. Memory controller hub 1616 alsocouples with an optional external graphics processor 1612, which maycommunicate with the one or more graphics processors 1608 in processors1602 to perform graphics and media operations.

In some embodiments, ICH 1630 enables peripherals to connect to memorydevice 1620 and processor 1602 via a high-speed I/O bus. The I/Operipherals include, but are not limited to, an audio controller 1646, afirmware interface 1628, a wireless transceiver 1626 (e.g., Wi-Fi,Bluetooth), a data storage device 1624 (e.g., hard disk drive, flashmemory, etc.), and a legacy I/O controller 1640 for coupling legacy(e.g., Personal System 2 (PS/2)) devices to the system. One or moreUniversal Serial Bus (USB) controllers 1642 connect input devices, suchas keyboard and mouse 1644 combinations. A network controller 1634 mayalso couple with ICH 1630. In some embodiments, a high-performancenetwork controller (not shown) couples with processor bus 1610. It willbe appreciated that the system 1600 shown is exemplary and not limiting,as other types of data processing systems that are differentlyconfigured may also be used. For example, the I/O controller hub 1630may be integrated within the one or more processor 1602, or the memorycontroller hub 1616 and I/O controller hub 1630 may be integrated into adiscreet external graphics processor, such as the external graphicsprocessor 1612.

FIG. 17 is a block diagram of an embodiment of a processor 1700 havingone or more processor cores 1702A-1702N, an integrated memory controller1714, and an integrated graphics processor 1708. Those elements of FIG.17 having the same reference numbers (or names) as the elements of anyother figure herein can operate or function in any manner similar tothat described elsewhere herein, but are not limited to such. Processor1700 can include additional cores up to and including additional core1702N represented by the dashed lined boxes. Each of processor cores1702A-1702N includes one or more internal cache units 1704A-1704N. Insome embodiments each processor core also has access to one or moreshared cached units 1706.

The internal cache units 1704A-1704N and shared cache units 1706represent a cache memory hierarchy within the processor 1700. The cachememory hierarchy may include at least one level of instruction and datacache within each processor core and one or more levels of sharedmid-level cache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), orother levels of cache, where the highest level of cache before externalmemory is classified as the LLC. In some embodiments, cache coherencylogic maintains coherency between the various cache units 1706 and1704A-1704N.

In some embodiments, processor 1700 may also include a set of one ormore bus controller units 1716 and a system agent core 1710. The one ormore bus controller units 1716 manage a set of peripheral buses, such asone or more Peripheral Component Interconnect buses (e.g., PCI, PCIExpress). System agent core 1710 provides management functionality forthe various processor components. In some embodiments, system agent core1710 includes one or more integrated memory controllers 1714 to manageaccess to various external memory devices (not shown).

In some embodiments, one or more of the processor cores 1702A-1702Ninclude support for simultaneous multi-threading. In such embodiment,the system agent core 1710 includes components for coordinating andoperating processor cores 1702A-1702N during multi-threaded processing.System agent core 1710 may additionally include a power control unit(PCU), which includes logic and components to regulate the power stateof processor cores 1702A-1702N and graphics processor 1708.

In some embodiments, processor 1700 additionally includes graphicsprocessor 1708 to execute graphics processing operations. In someembodiments, the graphics processor 1708 couples with the set of sharedcache units 1706, and the system agent core 1710, including the one ormore integrated memory controllers 1714. In some embodiments, a displaycontroller 1711 is coupled with the graphics processor 1708 to drivegraphics processor output to one or more coupled displays. In someembodiments, display controller 1711 may be a separate module coupledwith the graphics processor via at least one interconnect, or may beintegrated within the graphics processor 1708 or system agent core 1710.

In some embodiments, a ring based interconnect 1712 is used to couplethe internal components of the processor 1700. However, an alternativeinterconnect unit may be used, such as a point-to-point interconnect, aswitched interconnect, or other techniques, including techniques wellknown in the art. In some embodiments, graphics processor 1708 coupleswith the ring-based interconnect 1712 via an I/O link 1713.

The exemplary I/O link 1713 represents at least one of multiplevarieties of I/O interconnects, including an on-package I/O interconnectwhich facilitates communication between various processor components anda high-performance embedded memory module 1718, such as an eDRAM module.In some embodiments, each of the processor cores 1702A-1702N andgraphics processor 1708 use embedded memory modules 1718 as a sharedLast Level Cache.

In some embodiments, processor cores 1702A-1702N are homogenous coresexecuting the same instruction set architecture. In another embodiment,processor cores 1702A-1702N are heterogeneous in terms of instructionset architecture (ISA), where one or more of processor cores 1702A-1702Nexecute a first instruction set, while at least one of the other coresexecutes a subset of the first instruction set or a differentinstruction set. In one embodiment processor cores 1702A-1702N areheterogeneous in terms of microarchitecture, where one or more coreshaving a relatively higher power consumption couple with one or morepower cores having a lower power consumption. Additionally, processor1700 can be implemented on one or more chips or as an SoC integratedcircuit having the illustrated components, in addition to othercomponents.

FIG. 18 is a block diagram of a graphics processor 1800, which may be adiscrete graphics processing unit, or may be a graphics processorintegrated with a plurality of processing cores. In some embodiments,the graphics processor communicates via a memory mapped I/O interface toregisters on the graphics processor and with commands placed into theprocessor memory. In some embodiments, graphics processor 1800 includesa memory interface 1814 to access memory. Memory interface 1814 can bean interface to local memory, one or more internal caches, one or moreshared external caches, and/or to system memory.

In some embodiments, graphics processor 1800 also includes a displaycontroller 1802 to drive display output data to a display device 1820.Display controller 1802 includes hardware for one or more overlay planesfor the display and composition of multiple layers of video or userinterface elements. In some embodiments, graphics processor 1800includes a video codec engine 1806 to encode, decode, or transcode mediato, from, or between one or more media encoding formats, including, butnot limited to Moving Picture Experts Group (MPEG) formats such asMPEG-2, Advanced Video Coding (AVC) formats such as H.264/MPEG-4 AVC, aswell as the Society of Motion Picture & Television Engineers (SMPTE)421M/VC-1, and Joint Photographic Experts Group (JPEG) formats such asJPEG, and Motion JPEG (MJPEG) formats.

In some embodiments, graphics processor 1800 includes a block imagetransfer (BLIT) engine 1804 to perform two-dimensional (2D) rasterizeroperations including, for example, bit-boundary block transfers.However, in one embodiment, 2D graphics operations are performed usingone or more components of graphics processing engine (GPE) 1810. In someembodiments, GPE 1810 is a compute engine for performing graphicsoperations, including three-dimensional (3D) graphics operations andmedia operations.

In some embodiments, GPE 1810 includes a 3D pipeline 1812 for performing3D operations, such as rendering three-dimensional images and scenesusing processing functions that act upon 3D primitive shapes (e.g.,rectangle, triangle, etc.). The 3D pipeline 1812 includes programmableand fixed function elements that perform various tasks within theelement and/or spawn execution threads to a 3D/Media sub-system 1815.While 3D pipeline 1812 can be used to perform media operations, anembodiment of GPE 1810 also includes a media pipeline 1816 that isspecifically used to perform media operations, such as videopost-processing and image enhancement.

In some embodiments, media pipeline 1816 includes fixed function orprogrammable logic units to perform one or more specialized mediaoperations, such as video decode acceleration, video de-interlacing, andvideo encode acceleration in place of, or on behalf of video codecengine 1806. In some embodiments, media pipeline 1816 additionallyincludes a thread spawning unit to spawn threads for execution on3D/Media sub-system 1815. The spawned threads perform computations forthe media operations on one or more graphics execution units included in3D/Media sub-system 1815.

In some embodiments, 3D/Media sub-system 1815 includes logic forexecuting threads spawned by 3D pipeline 1812 and media pipeline 1816.In one embodiment, the pipelines send thread execution requests to3D/Media sub-system 1815, which includes thread dispatch logic forarbitrating and dispatching the various requests to available threadexecution resources. The execution resources include an array ofgraphics execution units to process the 3D and media threads. In someembodiments, 3D/Media sub-system 1815 includes one or more internalcaches for thread instructions and data. In some embodiments, thesubsystem also includes shared memory, including registers andaddressable memory, to share data between threads and to store outputdata.

Graphics Processing Engine

FIG. 19 is a block diagram of a graphics processing engine 1910 of agraphics processor in accordance with some embodiments. In oneembodiment, the graphics processing engine (GPE) 1910 is a version ofthe GPE 1810 shown in FIG. 18. Elements of FIG. 19 having the samereference numbers (or names) as the elements of any other figure hereincan operate or function in any manner similar to that describedelsewhere herein, but are not limited to such. For example, the 3Dpipeline 1812 and media pipeline 1816 of FIG. 18 are illustrated. Themedia pipeline 1816 is optional in some embodiments of the GPE 1910 andmay not be explicitly included within the GPE 1910. For example and inat least one embodiment, a separate media and/or image processor iscoupled to the GPE 1910.

In some embodiments, GPE 1910 couples with or includes a commandstreamer 1903, which provides a command stream to the 3D pipeline 1812and/or media pipelines 1816. In some embodiments, command streamer 1903is coupled with memory, which can be system memory, or one or more ofinternal cache memory and shared cache memory. In some embodiments,command streamer 1903 receives commands from the memory and sends thecommands to 3D pipeline 1812 and/or media pipeline 1816. The commandsare directives fetched from a ring buffer, which stores commands for the3D pipeline 1812 and media pipeline 1816. In one embodiment, the ringbuffer can additionally include batch command buffers storing batches ofmultiple commands. The commands for the 3D pipeline 1812 can alsoinclude references to data stored in memory, such as but not limited tovertex and geometry data for the 3D pipeline 1812 and/or image data andmemory objects for the media pipeline 1816. The 3D pipeline 1812 andmedia pipeline 1816 process the commands and data by performingoperations via logic within the respective pipelines or by dispatchingone or more execution threads to a graphics core array 1914.

In various embodiments the 3D pipeline 1812 can execute one or moreshader programs, such as vertex shaders, geometry shaders, pixelshaders, fragment shaders, compute shaders, or other shader programs, byprocessing the instructions and dispatching execution threads to thegraphics core array 1914. The graphics core array 1914 provides aunified block of execution resources. Multi-purpose execution logic(e.g., execution units) within the graphics core array 1914 includessupport for various 3D API shader languages and can execute multiplesimultaneous execution threads associated with multiple shaders.

In some embodiments the graphics core array 1914 also includes executionlogic to perform media functions, such as video and/or image processing.In one embodiment, the execution units additionally includegeneral-purpose logic that is programmable to perform parallel generalpurpose computational operations, in addition to graphics processingoperations. The general-purpose logic can perform processing operationsin parallel or in conjunction with general purpose logic within theprocessor core(s) 1607 of FIG. 16 or processor core 1702A-1702N as inFIG. 17.

Output data generated by threads executing on the graphics core array1914 can output data to memory in a unified return buffer (URB) 1918.The URB 1918 can store data for multiple threads. In some embodimentsthe URB 1918 may be used to send data between different threadsexecuting on the graphics core array 1914. In some embodiments the URB1918 may additionally be used for synchronization between threads on thegraphics core array and fixed function logic within the shared functionlogic 1920.

In some embodiments, graphics core array 1914 is scalable, such that thearray includes a variable number of graphics cores, each having avariable number of execution units based on the target power andperformance level of GPE 1910. In one embodiment the execution resourcesare dynamically scalable, such that execution resources may be enabledor disabled as needed.

The graphics core array 1914 couples with shared function logic 1920that includes multiple resources that are shared between the graphicscores in the graphics core array. The shared functions within the sharedfunction logic 1920 are hardware logic units that provide specializedsupplemental functionality to the graphics core array 1914. In variousembodiments, shared function logic 1920 includes but is not limited tosampler 1921, math 1922, and inter-thread communication (ITC) 1923logic. Additionally, some embodiments implement one or more cache(s)1925 within the shared function logic 1920. A shared function isimplemented where the demand for a given specialized function isinsufficient for inclusion within the graphics core array 1914. Insteada single instantiation of that specialized function is implemented as astand-alone entity in the shared function logic 1920 and shared amongthe execution resources within the graphics core array 1914. The preciseset of functions that are shared between the graphics core array 1914and included within the graphics core array 1914 varies betweenembodiments.

FIG. 20 is a block diagram of another embodiment of a graphics processor2000. Elements of FIG. 20 having the same reference numbers (or names)as the elements of any other figure herein can operate or function inany manner similar to that described elsewhere herein, but are notlimited to such.

In some embodiments, graphics processor 2000 includes a ringinterconnect 2002, a pipeline front-end 2004, a media engine 2037, andgraphics cores 2080A-2080N. In some embodiments, ring interconnect 2002couples the graphics processor to other processing units, includingother graphics processors or one or more general-purpose processorcores. In some embodiments, the graphics processor is one of manyprocessors integrated within a multi-core processing system.

In some embodiments, graphics processor 2000 receives batches ofcommands via ring interconnect 2002. The incoming commands areinterpreted by a command streamer 2003 in the pipeline front-end 2004.In some embodiments, graphics processor 2000 includes scalable executionlogic to perform 3D geometry processing and media processing via thegraphics core(s) 2080A-2080N. For 3D geometry processing commands,command streamer 2003 supplies commands to geometry pipeline 2036. Forat least some media processing commands, command streamer 2003 suppliesthe commands to a video front end 2034, which couples with a mediaengine 2037. In some embodiments, media engine 2037 includes a VideoQuality Engine (VQE) 2030 for video and image post-processing and amulti-format encode/decode (MFX) 2033 engine to providehardware-accelerated media data encode and decode. In some embodiments,geometry pipeline 2036 and media engine 2037 each generate executionthreads for the thread execution resources provided by at least onegraphics core 2080A.

In some embodiments, graphics processor 2000 includes scalable threadexecution resources featuring modular cores 2080A-2080N (sometimesreferred to as core slices), each having multiple sub-cores 2050A-550N,2060A-2060N (sometimes referred to as core sub-slices). In someembodiments, graphics processor 2000 can have any number of graphicscores 2080A through 2080N. In some embodiments, graphics processor 2000includes a graphics core 2080A having at least a first sub-core 2050Aand a second sub-core 2060A. In other embodiments, the graphicsprocessor is a low power processor with a single sub-core (e.g., 2050A).In some embodiments, graphics processor 2000 includes multiple graphicscores 2080A-2080N, each including a set of first sub-cores 2050A-2050Nand a set of second sub-cores 2060A-2060N. Each sub-core in the set offirst sub-cores 2050A-2050N includes at least a first set of executionunits 2052A-2052N and media/texture samplers 2054A-2054N. Each sub-corein the set of second sub-cores 2060A-2060N includes at least a secondset of execution units 2062A-2062N and samplers 2064A-2064N. In someembodiments, each sub-core 2050A-2050N, 2060A-2060N shares a set ofshared resources 2070A-2070N. In some embodiments, the shared resourcesinclude shared cache memory and pixel operation logic. Other sharedresources may also be included in the various embodiments of thegraphics processor.

Execution Units

FIG. 21 illustrates thread execution logic 2100 including an array ofprocessing elements employed in some embodiments of a GPE. Elements ofFIG. 21 having the same reference numbers (or names) as the elements ofany other figure herein can operate or function in any manner similar tothat described elsewhere herein, but are not limited to such.

In some embodiments, thread execution logic 2100 includes a shaderprocessor 2102, a thread dispatcher 2104, instruction cache 2106, ascalable execution unit array including a plurality of execution units2108A-2108N, a sampler 2110, a data cache 2112, and a data port 2114. Inone embodiment the scalable execution unit array can dynamically scaleby enabling or disabling one or more execution units (e.g., any ofexecution unit 2108A, 2108B, 2108C, 2108D, through 2108N-1 and 2108N)based on the computational requirements of a workload. In one embodimentthe included components are interconnected via an interconnect fabricthat links to each of the components. In some embodiments, threadexecution logic 2100 includes one or more connections to memory, such assystem memory or cache memory, through one or more of instruction cache2106, data port 2114, sampler 2110, and execution units 2108A-2108N. Insome embodiments, each execution unit (e.g. 2108A) is a stand-aloneprogrammable general purpose computational unit that is capable ofexecuting multiple simultaneous hardware threads while processingmultiple data elements in parallel for each thread. In variousembodiments, the array of execution units 2108A-2108N is scalable toinclude any number individual execution units.

In some embodiments, the execution units 2108A-2108N are primarily usedto execute shader programs. A shader processor 2102 can process thevarious shader programs and dispatch execution threads associated withthe shader programs via a thread dispatcher 2104. In one embodiment thethread dispatcher includes logic to arbitrate thread initiation requestsfrom the graphics and media pipelines and instantiate the requestedthreads on one or more execution unit in the execution units2108A-2108N. For example, the geometry pipeline (e.g., 2036 of FIG. 20)can dispatch vertex, tessellation, or geometry shaders to the threadexecution logic 2100 (FIG. 21) for processing. In some embodiments,thread dispatcher 2104 can also process runtime thread spawning requestsfrom the executing shader programs.

In some embodiments, the execution units 2108A-2108N support aninstruction set that includes native support for many standard 3Dgraphics shader instructions, such that shader programs from graphicslibraries (e.g., Direct 3D and OpenGL) are executed with a minimaltranslation. The execution units support vertex and geometry processing(e.g., vertex programs, geometry programs, vertex shaders), pixelprocessing (e.g., pixel shaders, fragment shaders) and general-purposeprocessing (e.g., compute and media shaders). Each of the executionunits 2108A-2108N is capable of multi-issue single instruction multipledata (SIMD) execution and multi-threaded operation enables an efficientexecution environment in the face of higher latency memory accesses.Each hardware thread within each execution unit has a dedicatedhigh-bandwidth register file and associated independent thread-state.Execution is multi-issue per clock to pipelines capable of integer,single and double precision floating point operations, SIMD branchcapability, logical operations, transcendental operations, and othermiscellaneous operations. While waiting for data from memory or one ofthe shared functions, dependency logic within the execution units2108A-2108N causes a waiting thread to sleep until the requested datahas been returned. While the waiting thread is sleeping, hardwareresources may be devoted to processing other threads. For example,during a delay associated with a vertex shader operation, an executionunit can perform operations for a pixel shader, fragment shader, oranother type of shader program, including a different vertex shader.

Each execution unit in execution units 2108A-2108N operates on arrays ofdata elements. The number of data elements is the “execution size,” orthe number of channels for the instruction. An execution channel is alogical unit of execution for data element access, masking, and flowcontrol within instructions. The number of channels may be independentof the number of physical Arithmetic Logic Units (ALUs) or FloatingPoint Units (FPUs) for a particular graphics processor. In someembodiments, execution units 2108A-2108N support integer andfloating-point data types.

The execution unit instruction set includes SIMD instructions. Thevarious data elements can be stored as a packed data type in a registerand the execution unit will process the various elements based on thedata size of the elements. For example, when operating on a 256-bit widevector, the 256 bits of the vector are stored in a register and theexecution unit operates on the vector as four separate 64-bit packeddata elements (Quad-Word (QW) size data elements), eight separate 32-bitpacked data elements (Double Word (DW) size data elements), sixteenseparate 16-bit packed data elements (Word (W) size data elements), orthirty-two separate 8-bit data elements (byte (B) size data elements).However, different vector widths and register sizes are possible.

One or more internal instruction caches (e.g., 2106) are included in thethread execution logic 2100 to cache thread instructions for theexecution units. In some embodiments, one or more data caches (e.g.,2112) are included to cache thread data during thread execution. In someembodiments, a sampler 2110 is included to provide texture sampling for3D operations and media sampling for media operations. In someembodiments, sampler 2110 includes specialized texture or media samplingfunctionality to process texture or media data during the samplingprocess before providing the sampled data to an execution unit.

During execution, the graphics and media pipelines send threadinitiation requests to thread execution logic 2100 via thread spawningand dispatch logic. Once a group of geometric objects has been processedand rasterized into pixel data, pixel processor logic (e.g., pixelshader logic, fragment shader logic, etc.) within the shader processor2102 is invoked to further compute output information and cause resultsto be written to output surfaces (e.g., color buffers, depth buffers,stencil buffers, etc.). In some embodiments, a pixel shader or fragmentshader calculates the values of the various vertex attributes that areto be interpolated across the rasterized object. In some embodiments,pixel processor logic within the shader processor 2102 then executes anapplication programming interface (API)-supplied pixel or fragmentshader program. To execute the shader program, the shader processor 2102dispatches threads to an execution unit (e.g., 2108A) via threaddispatcher 2104. In some embodiments, shader processor 2102 uses texturesampling logic in the sampler 2110 to access texture data in texturemaps stored in memory. Arithmetic operations on the texture data and theinput geometry data compute pixel color data for each geometricfragment, or discards one or more pixels from further processing.

In some embodiments, the data port 2114 provides a memory accessmechanism for the thread execution logic 2100 output processed data tomemory for processing on a graphics processor output pipeline. In someembodiments, the data port 2114 includes or couples to one or more cachememories (e.g., data cache 2112) to cache data for memory access via thedata port.

FIG. 22 is a block diagram illustrating graphics processor instructionformats 2200 according to some embodiments. In one or more embodiment,the graphics processor execution units support an instruction set havinginstructions in multiple formats. The solid lined boxes illustrate thecomponents that are generally included in an execution unit instruction,while the dashed lines include components that are optional or that areonly included in a sub-set of the instructions. In some embodiments,instruction format 2200 described and illustrated aremacro-instructions, in that they are instructions supplied to theexecution unit, as opposed to micro-operations resulting frominstruction decode once the instruction is processed.

In some embodiments, the graphics processor execution units nativelysupport instructions in a 128-bit instruction format 2210. A 64-bitcompacted instruction format 2230 is available for some instructionsbased on the selected instruction, instruction options, and number ofoperands. The native 128-bit instruction format 710 provides access toall instruction options, while some options and operations arerestricted in the 64-bit format 2230. The native instructions availablein the 64-bit format 2230 vary by embodiment. In some embodiments, theinstruction is compacted in part using a set of index values in an indexfield 2213. The execution unit hardware references a set of compactiontables based on the index values and uses the compaction table outputsto reconstruct a native instruction in the 128-bit instruction format2210.

For each format, instruction opcode 2212 defines the operation that theexecution unit is to perform. The execution units execute eachinstruction in parallel across the multiple data elements of eachoperand. For example, in response to an add instruction the executionunit performs a simultaneous add operation across each color channelrepresenting a texture element or picture element. By default, theexecution unit performs each instruction across all data channels of theoperands. In some embodiments, instruction control field 2214 enablescontrol over certain execution options, such as channels selection(e.g., predication) and data channel order (e.g., swizzle). Forinstructions in the 128-bit instruction format 2210 an exec-size field2216 limits the number of data channels that will be executed inparallel. In some embodiments, exec-size field 2216 is not available foruse in the 64-bit compact instruction format 2230.

Some execution unit instructions have up to three operands including twosource operands, src0 2220, src1 2222, and one destination 2218. In someembodiments, the execution units support dual destination instructions,where one of the destinations is implied. Data manipulation instructionscan have a third source operand (e.g., SRC2 2224), where the instructionopcode 2212 determines the number of source operands. An instruction'slast source operand can be an immediate (e.g., hard-coded) value passedwith the instruction.

In some embodiments, the 128-bit instruction format 2210 includes anaccess/address mode field 2226 specifying, for example, whether directregister addressing mode or indirect register addressing mode is used.When direct register addressing mode is used, the register address ofone or more operands is directly provided by bits in the instruction.

In some embodiments, the 128-bit instruction format 2210 includes anaccess/address mode field 2226, which specifies an address mode and/oran access mode for the instruction. In one embodiment the access mode isused to define a data access alignment for the instruction. Someembodiments support access modes including a 16-byte aligned access modeand a 1-byte aligned access mode, where the byte alignment of the accessmode determines the access alignment of the instruction operands. Forexample, when in a first mode, the instruction may use byte-alignedaddressing for source and destination operands and when in a secondmode, the instruction may use 16-byte-aligned addressing for all sourceand destination operands.

In one embodiment, the address mode portion of the access/address modefield 2226 determines whether the instruction is to use direct orindirect addressing. When direct register addressing mode is used bitsin the instruction directly provide the register address of one or moreoperands. When indirect register addressing mode is used, the registeraddress of one or more operands may be computed based on an addressregister value and an address immediate field in the instruction.

In some embodiments instructions are grouped based on opcode 2212bit-fields to simplify Opcode decode 2240. For an 8-bit opcode, bits 4,5, and 6 allow the execution unit to determine the type of opcode. Theprecise opcode grouping shown is merely an example. In some embodiments,a move and logic opcode group 2242 includes data movement and logicinstructions (e.g., move (mov), compare (cmp)). In some embodiments,move and logic opcode group 2242 shares the five most significant bits(MSB), where move (mov) instructions are in the form of 0000xxxxb andlogic instructions are in the form of 0001xxxxb. A flow controlinstruction group 2244 (e.g., call, jump (jmp)) includes instructions inthe form of 0010xxxxb (e.g., 0x20). A miscellaneous instruction group2246 includes a mix of instructions, including synchronizationinstructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). Aparallel math instruction group 2248 includes component-wise arithmeticinstructions (e.g., add, multiply (mul)) in the form of 0100xxxxb (e.g.,0x40). The parallel math instruction group 2248 performs the arithmeticoperations in parallel across data channels. The vector math group 2250includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb(e.g., 0x50). The vector math group performs arithmetic such as dotproduct calculations on vector operands.

Graphics Pipeline

FIG. 23 is a block diagram of another embodiment of a graphics processor2300. Elements of FIG. 23 having the same reference numbers (or names)as the elements of any other figure herein can operate or function inany manner similar to that described elsewhere herein, but are notlimited to such.

In some embodiments, graphics processor 2300 includes a graphicspipeline 2320, a media pipeline 2330, a display engine 2340, threadexecution logic 2350, and a render output pipeline 2370. In someembodiments, graphics processor 2300 is a graphics processor within amulti-core processing system that includes one or more general purposeprocessing cores. The graphics processor is controlled by registerwrites to one or more control registers (not shown) or via commandsissued to graphics processor 2300 via a ring interconnect 2302. In someembodiments, ring interconnect 2302 couples graphics processor 2300 toother processing components, such as other graphics processors orgeneral-purpose processors. Commands from ring interconnect 2302 areinterpreted by a command streamer 2303, which supplies instructions toindividual components of graphics pipeline 2320 or media pipeline 2330.

In some embodiments, command streamer 2303 directs the operation of avertex fetcher 2305 that reads vertex data from memory and executesvertex-processing commands provided by command streamer 2303. In someembodiments, vertex fetcher 2305 provides vertex data to a vertex shader2307, which performs coordinate space transformation and lightingoperations to each vertex. In some embodiments, vertex fetcher 2305 andvertex shader 2307 execute vertex-processing instructions by dispatchingexecution threads to execution units 2352A-2352B via a thread dispatcher2331.

In some embodiments, execution units 2352A-2352B are an array of vectorprocessors having an instruction set for performing graphics and mediaoperations. In some embodiments, execution units 2352A-2352B have anattached L1 cache 2351 that is specific for each array or shared betweenthe arrays. The cache can be configured as a data cache, an instructioncache, or a single cache that is partitioned to contain data andinstructions in different partitions.

In some embodiments, graphics pipeline 2320 includes tessellationcomponents to perform hardware-accelerated tessellation of 3D objects.In some embodiments, a programmable hull shader 811 configures thetessellation operations. A programmable domain shader 817 providesback-end evaluation of tessellation output. A tessellator 2313 operatesat the direction of hull shader 2311 and contains special purpose logicto generate a set of detailed geometric objects based on a coarsegeometric model that is provided as input to graphics pipeline 2320. Insome embodiments, if tessellation is not used, tessellation components(e.g., hull shader 2311, tessellator 2313, and domain shader 2317) canbe bypassed.

In some embodiments, complete geometric objects can be processed by ageometry shader 2319 via one or more threads dispatched to executionunits 2352A-2352B, or can proceed directly to the clipper 2329. In someembodiments, the geometry shader operates on entire geometric objects,rather than vertices or patches of vertices as in previous stages of thegraphics pipeline. If the tessellation is disabled the geometry shader2319 receives input from the vertex shader 2307. In some embodiments,geometry shader 2319 is programmable by a geometry shader program toperform geometry tessellation if the tessellation units are disabled.

Before rasterization, a clipper 2329 processes vertex data. The clipper2329 may be a fixed function clipper or a programmable clipper havingclipping and geometry shader functions. In some embodiments, arasterizer and depth test component 2373 in the render output pipeline2370 dispatches pixel shaders to convert the geometric objects intotheir per pixel representations. In some embodiments, pixel shader logicis included in thread execution logic 2350. In some embodiments, anapplication can bypass the rasterizer and depth test component 2373 andaccess un-rasterized vertex data via a stream out unit 2323.

The graphics processor 2300 has an interconnect bus, interconnectfabric, or some other interconnect mechanism that allows data andmessage passing amongst the major components of the processor. In someembodiments, execution units 2352A-2352B and associated cache(s) 2351,texture and media sampler 2354, and texture/sampler cache 2358interconnect via a data port 2356 to perform memory access andcommunicate with render output pipeline components of the processor. Insome embodiments, sampler 2354, caches 2351, 2358 and execution units2352A-2352B each have separate memory access paths.

In some embodiments, render output pipeline 2370 contains a rasterizerand depth test component 2373 that converts vertex-based objects into anassociated pixel-based representation. In some embodiments, therasterizer logic includes a windower/masker unit to perform fixedfunction triangle and line rasterization. An associated render cache2378 and depth cache 2379 are also available in some embodiments. Apixel operations component 2377 performs pixel-based operations on thedata, though in some instances, pixel operations associated with 2Doperations (e.g. bit block image transfers with blending) are performedby the 2D engine 2341, or substituted at display time by the displaycontroller 2343 using overlay display planes. In some embodiments, ashared L3 cache 2375 is available to all graphics components, allowingthe sharing of data without the use of main system memory.

In some embodiments, graphics processor media pipeline 2330 includes amedia engine 2337 and a video front-end 2334. In some embodiments, videofront-end 2334 receives pipeline commands from the command streamer2303. In some embodiments, media pipeline 2330 includes a separatecommand streamer. In some embodiments, video front-end 2334 processesmedia commands before sending the command to the media engine 2337. Insome embodiments, media engine 2337 includes thread spawningfunctionality to spawn threads for dispatch to thread execution logic2350 via thread dispatcher 2331.

In some embodiments, graphics processor 2300 includes a display engine2340. In some embodiments, display engine 2340 is external to graphicsprocessor 2300 and couples with the graphics processor via the ringinterconnect 2302, or some other interconnect bus or fabric. In someembodiments, display engine 2340 includes a 2D engine 2341 and a displaycontroller 2343. In some embodiments, display engine 2340 containsspecial purpose logic capable of operating independently of the 3Dpipeline. In some embodiments, display controller 2343 couples with adisplay device (not shown), which may be a system integrated displaydevice, as in a laptop computer, or an external display device attachedvia a display device connector.

In some embodiments, graphics pipeline 2320 and media pipeline 2330 areconfigurable to perform operations based on multiple graphics and mediaprogramming interfaces and are not specific to any one applicationprogramming interface (API). In some embodiments, driver software forthe graphics processor translates API calls that are specific to aparticular graphics or media library into commands that can be processedby the graphics processor. In some embodiments, support is provided forthe Open Graphics Library (OpenGL), Open Computing Language (OpenCL),and/or Vulkan graphics and compute API, all from the Khronos Group. Insome embodiments, support may also be provided for the Direct3D libraryfrom the Microsoft Corporation. In some embodiments, a combination ofthese libraries may be supported. Support may also be provided for theOpen Source Computer Vision Library (OpenCV). A future API with acompatible 3D pipeline would also be supported if a mapping can be madefrom the pipeline of the future API to the pipeline of the graphicsprocessor.

Graphics Pipeline Programming

FIG. 24A is a block diagram illustrating a graphics processor commandformat 2400 according to some embodiments. FIG. 24B is a block diagramillustrating a graphics processor command sequence 2410 according to anembodiment. The solid lined boxes in FIG. 24A illustrate the componentsthat are generally included in a graphics command while the dashed linesinclude components that are optional or that are only included in asub-set of the graphics commands. The exemplary graphics processorcommand format 2400 of FIG. 24A includes data fields to identify atarget client 2402 of the command, a command operation code (opcode)2404, and the relevant data field 2406 for the command. A sub-opcode2405 and a command size 2408 are also included in some commands.

In some embodiments, client 2402 specifies the client unit of thegraphics device that processes the command data. In some embodiments, agraphics processor command parser examines the client field of eachcommand to condition the further processing of the command and route thecommand data to the appropriate client unit. In some embodiments, thegraphics processor client units include a memory interface unit, arender unit, a 2D unit, a 3D unit, and a media unit. Each client unithas a corresponding processing pipeline that processes the commands.Once the command is received by the client unit, the client unit readsthe opcode 2404 and, if present, sub-opcode 2405 to determine theoperation to perform. The client unit performs the command usinginformation in data field 2406. For some commands an explicit commandsize 2408 is expected to specify the size of the command. In someembodiments, the command parser automatically determines the size of atleast some of the commands based on the command opcode. In someembodiments commands are aligned via multiples of a double word.

The flow diagram in FIG. 24B shows an exemplary graphics processorcommand sequence 2410. In some embodiments, software or firmware of adata processing system that features an embodiment of a graphicsprocessor uses a version of the command sequence shown to set up,execute, and terminate a set of graphics operations. A sample commandsequence is shown and described for purposes of example only asembodiments are not limited to these specific commands or to thiscommand sequence. Moreover, the commands may be issued as batch ofcommands in a command sequence, such that the graphics processor willprocess the sequence of commands in at least partially concurrence.

In some embodiments, the graphics processor command sequence 2410 maybegin with a pipeline flush command 2412 to cause any active graphicspipeline to complete the currently pending commands for the pipeline. Insome embodiments, the 3D pipeline 2422 and the media pipeline 2424 donot operate concurrently. The pipeline flush is performed to cause theactive graphics pipeline to complete any pending commands. In responseto a pipeline flush, the command parser for the graphics processor willpause command processing until the active drawing engines completepending operations and the relevant read caches are invalidated.Optionally, any data in the render cache that is marked ‘dirty’ can beflushed to memory. In some embodiments, pipeline flush command 2412 canbe used for pipeline synchronization or before placing the graphicsprocessor into a low power state.

In some embodiments, a pipeline select command 2413 is used when acommand sequence requires the graphics processor to explicitly switchbetween pipelines. In some embodiments, a pipeline select command 2413is required only once within an execution context before issuingpipeline commands unless the context is to issue commands for bothpipelines. In some embodiments, a pipeline flush command 2412 isrequired immediately before a pipeline switch via the pipeline selectcommand 2413.

In some embodiments, a pipeline control command 2414 configures agraphics pipeline for operation and is used to program the 3D pipeline2422 and the media pipeline 2424. In some embodiments, pipeline controlcommand 2414 configures the pipeline state for the active pipeline. Inone embodiment, the pipeline control command 2414 is used for pipelinesynchronization and to clear data from one or more cache memories withinthe active pipeline before processing a batch of commands.

In some embodiments, return buffer state commands 2416 are used toconfigure a set of return buffers for the respective pipelines to writedata. Some pipeline operations require the allocation, selection, orconfiguration of one or more return buffers into which the operationswrite intermediate data during processing. In some embodiments, thegraphics processor also uses one or more return buffers to store outputdata and to perform cross thread communication. In some embodiments, thereturn buffer state 2416 includes selecting the size and number ofreturn buffers to use for a set of pipeline operations.

The remaining commands in the command sequence differ based on theactive pipeline for operations. Based on a pipeline determination 2420,the command sequence is tailored to the 3D pipeline 2422 beginning withthe 3D pipeline state 2430 or the media pipeline 2424 beginning at themedia pipeline state 2440.

The commands to configure the 3D pipeline state 2430 include 3D statesetting commands for vertex buffer state, vertex element state, constantcolor state, depth buffer state, and other state variables that are tobe configured before 3D primitive commands are processed. The values ofthese commands are determined at least in part based on the particular3D API in use. In some embodiments, 3D pipeline state 2430 commands arealso able to selectively disable or bypass certain pipeline elements ifthose elements will not be used.

In some embodiments, 3D primitive 2432 command is used to submit 3Dprimitives to be processed by the 3D pipeline. Commands and associatedparameters that are passed to the graphics processor via the 3Dprimitive 2432 command are forwarded to the vertex fetch function in thegraphics pipeline. The vertex fetch function uses the 3D primitive 2432command data to generate vertex data structures. The vertex datastructures are stored in one or more return buffers. In someembodiments, 3D primitive 2432 command is used to perform vertexoperations on 3D primitives via vertex shaders. To process vertexshaders, 3D pipeline 2422 dispatches shader execution threads tographics processor execution units.

In some embodiments, 3D pipeline 2422 is triggered via an execute 2434command or event. In some embodiments, a register write triggers commandexecution. In some embodiments execution is triggered via a ‘go’ or‘kick’ command in the command sequence. In one embodiment, commandexecution is triggered using a pipeline synchronization command to flushthe command sequence through the graphics pipeline. The 3D pipeline willperform geometry processing for the 3D primitives. Once operations arecomplete, the resulting geometric objects are rasterized and the pixelengine colors the resulting pixels. Additional commands to control pixelshading and pixel back end operations may also be included for thoseoperations.

In some embodiments, the graphics processor command sequence 2410follows the media pipeline 2424 path when performing media operations.In general, the specific use and manner of programming for the mediapipeline 2424 depends on the media or compute operations to beperformed. Specific media decode operations may be offloaded to themedia pipeline during media decode. In some embodiments, the mediapipeline can also be bypassed and media decode can be performed in wholeor in part using resources provided by one or more general purposeprocessing cores. In one embodiment, the media pipeline also includeselements for general-purpose graphics processor unit (GPGPU) operations,where the graphics processor is used to perform SIMD vector operationsusing computational shader programs that are not explicitly related tothe rendering of graphics primitives.

In some embodiments, media pipeline 2424 is configured in a similarmanner as the 3D pipeline 2422. A set of commands to configure the mediapipeline state 2440 are dispatched or placed into a command queue beforethe media object commands 2442. In some embodiments, the commands forthe media pipeline state 2440 include data to configure the mediapipeline elements that will be used to process the media objects. Thisincludes data to configure the video decode and video encode logicwithin the media pipeline, such as encode or decode format. In someembodiments, commands for the media pipeline state 2440 enable supportthe use of one or more pointers to “indirect” state elements thatcontain a batch of state settings.

In some embodiments, media object commands 2442 supply pointers to mediaobjects for processing by the media pipeline. The media objects includememory buffers containing video data to be processed. In someembodiments, all media pipeline states must be valid before issuing amedia object command 2442. Once the pipeline state is configured andmedia object commands 2442 are queued, the media pipeline 2424 istriggered via an execute command 2444 or an equivalent execute event(e.g., register write). Output from media pipeline 2424 may then be postprocessed by operations provided by the 3D pipeline 2422 or the mediapipeline 2424. In some embodiments, GPGPU operations are configured andexecuted in a similar manner as media operations.

Graphics Software Architecture

FIG. 25 illustrates exemplary graphics software architecture for a dataprocessing system 2500 according to some embodiments. In someembodiments, software architecture includes a 3D graphics application2510, an operating system 2520, and at least one processor 2530. In someembodiments, processor 2530 includes a graphics processor 2532 and oneor more general-purpose processor core(s) 2534. The graphics application2510 and operating system 2520 each execute in the system memory 2550 ofthe data processing system.

In some embodiments, 3D graphics application 2510 contains one or moreshader programs including shader instructions 2512. The shader languageinstructions may be in a high-level shader language, such as the HighLevel Shader Language (HLSL) or the OpenGL Shader Language (GLSL). Theapplication also includes executable instructions 2514 in a machinelanguage suitable for execution by the general-purpose processor core(s)2534. The application also includes graphics objects 2516 defined byvertex data.

In some embodiments, operating system 2520 is a Microsoft® Windows®operating system from the Microsoft Corporation, a proprietary UNIX-likeoperating system, or an open source UNIX-like operating system using avariant of the Linux kernel. The operating system 2520 can support agraphics API 2522 such as the Direct3D API, the OpenGL API, or theVulkan API. When the Direct3D API is in use, the operating system 2520uses a front-end shader compiler 2524 to compile any shader instructions2512 in HLSL into a lower-level shader language. The compilation may bea just-in-time (JIT) compilation or the application can perform shaderpre-compilation. In some embodiments, high-level shaders are compiledinto low-level shaders during the compilation of the 3D graphicsapplication 2510. In some embodiments, the shader instructions 2512 areprovided in an intermediate form, such as a version of the StandardPortable Intermediate Representation (SPIR) used by the Vulkan API.

In some embodiments, user mode graphics driver 2526 contains a back-endshader compiler 2527 to convert the shader instructions 2512 into ahardware specific representation. When the OpenGL API is in use, shaderinstructions 2512 in the GLSL high-level language are passed to a usermode graphics driver 2526 for compilation. In some embodiments, usermode graphics driver 2526 uses operating system kernel mode functions2528 to communicate with a kernel mode graphics driver 2529. In someembodiments, kernel mode graphics driver 2529 communicates with graphicsprocessor 2532 to dispatch commands and instructions.

IP Core Implementations

One or more aspects of at least one embodiment may be implemented byrepresentative code stored on a machine-readable medium which representsand/or defines logic within an integrated circuit such as a processor.For example, the machine-readable medium may include instructions whichrepresent various logic within the processor. When read by a machine,the instructions may cause the machine to fabricate the logic to performthe techniques described herein. Such representations, known as “IPcores,” are reusable units of logic for an integrated circuit that maybe stored on a tangible, machine-readable medium as a hardware modelthat describes the structure of the integrated circuit. The hardwaremodel may be supplied to various customers or manufacturing facilities,which load the hardware model on fabrication machines that manufacturethe integrated circuit. The integrated circuit may be fabricated suchthat the circuit performs operations described in association with anyof the embodiments described herein.

FIG. 26 is a block diagram illustrating an IP core development system2600 that may be used to manufacture an integrated circuit to performoperations according to an embodiment. The IP core development system2600 may be used to generate modular, re-usable designs that can beincorporated into a larger design or used to construct an entireintegrated circuit (e.g., an SOC integrated circuit). A design facility2630 can generate a software simulation 2610 of an IP core design in ahigh level programming language (e.g., C/C++). The software simulation2610 can be used to design, test, and verify the behavior of the IP coreusing a simulation model 2612. The simulation model 2612 may includefunctional, behavioral, and/or timing simulations. A register transferlevel (RTL) design 2615 can then be created or synthesized from thesimulation model 2612. The RTL design 2615 is an abstraction of thebehavior of the integrated circuit that models the flow of digitalsignals between hardware registers, including the associated logicperformed using the modeled digital signals. In addition to an RTLdesign 2615, lower-level designs at the logic level or transistor levelmay also be created, designed, or synthesized. Thus, the particulardetails of the initial design and simulation may vary.

The RTL design 2615 or equivalent may be further synthesized by thedesign facility into a hardware model 2620, which may be in a hardwaredescription language (HDL), or some other representation of physicaldesign data. The HDL may be further simulated or tested to verify the IPcore design. The IP core design can be stored for delivery to a 3^(rd)party fabrication facility 2665 using non-volatile memory 2640 (e.g.,hard disk, flash memory, or any non-volatile storage medium).Alternatively, the IP core design may be transmitted (e.g., via theInternet) over a wired connection 2650 or wireless connection 2660. Thefabrication facility 2665 may then fabricate an integrated circuit thatis based at least in part on the IP core design. The fabricatedintegrated circuit can be configured to perform operations in accordancewith at least one embodiment described herein.

Exemplary System on a Chip Integrated Circuit

FIG. 27-29 illustrated exemplary integrated circuits and associatedgraphics processors that may be fabricated using one or more IP cores,according to various embodiments described herein. In addition to whatis illustrated, other logic and circuits may be included, includingadditional graphics processors/cores, peripheral interface controllers,or general purpose processor cores.

FIG. 27 is a block diagram illustrating an exemplary system on a chipintegrated circuit 2700 that may be fabricated using one or more IPcores, according to an embodiment. Exemplary integrated circuit 2700includes one or more application processor(s) 2705 (e.g., CPUs), atleast one graphics processor 2710, and may additionally include an imageprocessor 2715 and/or a video processor 2720, any of which may be amodular IP core from the same or multiple different design facilities.Integrated circuit 2700 includes peripheral or bus logic including a USBcontroller 2725, UART controller 2730, an SPI/SDIO controller 2735, andan I²S/I²C controller 2740. Additionally, the integrated circuit caninclude a display device 2745 coupled to one or more of ahigh-definition multimedia interface (HDMI) controller 2750 and a mobileindustry processor interface (MIPI) display interface 2755. Storage maybe provided by a flash memory subsystem 2760 including flash memory anda flash memory controller. Memory interface may be provided via a memorycontroller 2765 for access to SDRAM or SRAM memory devices. Someintegrated circuits additionally include an embedded security engine2770.

FIG. 28 is a block diagram illustrating an exemplary graphics processor2810 of a system on a chip integrated circuit that may be fabricatedusing one or more IP cores, according to an embodiment. Graphicsprocessor 2810 can be a variant of the graphics processor 2710 of FIG.27. Graphics processor 2810 includes a vertex processor 2805 and one ormore fragment processor(s) 2815A-2815N (e.g., 2815A, 2815B, 2815C,2815D, through 2815N-1, and 2815N). Graphics processor 2810 can executedifferent shader programs via separate logic, such that the vertexprocessor 2805 is optimized to execute operations for vertex shaderprograms, while the one or more fragment processor(s) 2815A-2815Nexecute fragment (e.g., pixel) shading operations for fragment or pixelshader programs. The vertex processor 2805 performs the vertexprocessing stage of the 3D graphics pipeline and generates primitivesand vertex data. The fragment processor(s) 2815A-2815N use the primitiveand vertex data generated by the vertex processor 2805 to produce aframebuffer that is displayed on a display device. In one embodiment,the fragment processor(s) 2815A-2815N are optimized to execute fragmentshader programs as provided for in the OpenGL API, which may be used toperform similar operations as a pixel shader program as provided for inthe Direct 3D API.

Graphics processor 2810 additionally includes one or more memorymanagement units (MMUs) 2820A-2820B, cache(s) 2825A-2825B, and circuitinterconnect(s) 2830A-2830B. The one or more MMU(s) 2820A-2820B providefor virtual to physical address mapping for the graphics processor 2810,including for the vertex processor 2805 and/or fragment processor(s)2815A-2815N, which may reference vertex or image/texture data stored inmemory, in addition to vertex or image/texture data stored in the one ormore cache(s) 2825A-2825B. In one embodiment the one or more MMU(s)2820A-2820B may be synchronized with other MMUs within the system,including one or more MMUs associated with the one or more applicationprocessor(s) 2705, image processor 2715, and/or video processor 2720 ofFIG. 27, such that each processor 2705-2720 can participate in a sharedor unified virtual memory system. The one or more circuitinterconnect(s) 2830A-2830B enable graphics processor 2810 to interfacewith other IP cores within the SoC, either via an internal bus of theSoC or via a direct connection, according to embodiments.

FIG. 29 is a block diagram illustrating an additional exemplary graphicsprocessor 2910 of a system on a chip integrated circuit that may befabricated using one or more IP cores, according to an embodiment.Graphics processor 2910 can be a variant of the graphics processor 2710of FIG. 27. Graphics processor 2910 includes the one or more MMU(s)2820A-2820B, cache(s) 2825A-2825B, and circuit interconnect(s)2830A-2830B of the integrated circuit 2800 of FIG. 28.

Graphics processor 2910 includes one or more shader core(s) 2915A-2915N(e.g., 2915A, 2915B, 2915C, 2915D, 2915E, 2915F, through 2915N-1, and2915N), which provides for a unified shader core architecture in which asingle core or type or core can execute all types of programmable shadercode, including shader program code to implement vertex shaders,fragment shaders, and/or compute shaders. The exact number of shadercores present can vary among embodiments and implementations.Additionally, graphics processor 2910 includes an inter-core taskmanager 2905, which acts as a thread dispatcher to dispatch executionthreads to one or more shader core(s) 2915A-2915N and a tiling unit 2918to accelerate tiling operations for tile-based rendering, in whichrendering operations for a scene are subdivided in image space, forexample to exploit local spatial coherence within a scene or to optimizeuse of internal caches.

The following clauses and/or examples pertain to specific embodiments orexamples thereof. Specifics in the examples may be used anywhere in oneor more embodiments. The various features of the different embodimentsor examples may be variously combined with some features included andothers excluded to suit a variety of different applications. Examplesmay include subject matter such as a method, means for performing actsof the method, at least one machine-readable medium includinginstructions that, when performed by a machine cause the machine toperform acts of the method, or of an apparatus or system according toembodiments and examples described herein. Various components can be ameans for performing the operations or functions described.

One embodiment provides for a machine-learning accelerator comprising ageneral-purpose graphics processing unit including a multiprocessor toexecute parallel threads of an instruction stream, the multiprocessorincluding a compute unit, the compute unit including a set of functionalunits, each functional unit to execute at least one of the parallelthreads of the instruction stream. The compute unit includes computelogic configured to execute a single instruction to scale an inputtensor associated with a layer of a neural network according to a scalefactor, the input tensor stored in a floating-point data type, thecompute logic to scale the input tensor to enable a data distribution ofdata of the input tensor to be represented by a 16-bit floating pointdata type.

One embodiment includes a method implemented via a machine-learningaccelerator, the method comprising executing parallel threads of aparallel instruction stream, the parallel instruction stream includingat least one single instruction to perform a scaled tensor computeoperation; in response to the single instruction, scaling data of aninput tensor associated with a layer of a neural network according to ascale factor, executing one or more compute operations on scaled data ofthe input tensor, and re-scaling computed data of the compute operationsto generate re-scaled computed data; down-converting the re-scaledcomputed data; and storing down-converted re-scaled computed data to a16-bit floating-point data type.

One embodiment provides for a data processing system comprising anon-transitory machine-readable medium to store instructions forexecution by one or more processors of the data processing system; and ageneral-purpose graphics processing unit including instruction decodelogic to decode a single instruction including multiple operands into asingle decoded instruction, at least one of the multiple operandsassociated with input tensor data of a layer of a neural network, and acompute unit including compute logic configured to execute the singleinstruction to scale data of the input tensor to enable a datadistribution of data of the input tensor to be represented by a 16-bitfloating point data type.

One embodiment provides for a graphics processor comprising a memorycontroller, a level-two (L2) cache memory coupled with the memorycontroller, and a multiprocessor coupled with the memory controller. Themultiprocessor can have a single instruction, multiple thread (SIMT)architecture including hardware multithreading, where the multiprocessoris to execute parallel threads of instructions associated with a commandstream. The multiprocessor includes a set of functional units to executeat least one of the parallel threads of the instructions. The set offunctional units include a mixed precision tensor processor to performtensor computations to generate loss data, wherein the loss data isstored as a floating-point data type and scaled by a scaling factor toenable a data distribution of a gradient tensor generated based on theloss data to be represented by a 16-bit floating point data type.

In a further embodiment the mixed precision tensor processor is toperform tensor computations associated with a layer of a neural networkto generate the loss data. The tensor computations can include abackward propagation operation associated with the layer of the neuralnetwork. The multiprocessor can dynamically adjust the scaling factorbased on values within the gradient tensor. The scaling operations forthe loss data can include performing operations to increase a minimumvalue of the gradient tensor to above the minimum value representable bya 16-bit floating point data type and to select a scaling factor suchthat the maximum value of the gradient tensor is below the maximum valuerepresentable by the 16-bit floating point data type. In one embodimentthe graphics processor additionally includes a 3D memory stack coupledto the memory controller. The 3D memory stack can include high-bandwidthmemory (e.g., HBM, HBM2, etc.).

One embodiment provides for a non-transitory machine-readable medium tostore instructions to cause one or more processors to perform operationscomprising executing, on a graphics processor, parallel threads ofinstructions associated with a command stream via a multiprocessorcoupled with a memory controller. The multiprocessor can have a singleinstruction, multiple thread (SIMT) architecture including hardwaremultithreading, where the multiprocessor includes a set of functionalunits to execute at least one of the parallel threads of theinstructions, the set of functional units including a mixed precisiontensor processor. The operations can additionally include performing,via the mixed precision tensor processor, tensor computations associatedwith a layer of a neural network to generate loss data, the loss datastored in a floating-point format and scaling the loss data generatedvia the tensor computations by a scaling factor to enable a datadistribution of a gradient tensor generated based on the loss data to berepresented by a scaled gradient tensor, the scaled gradient tensorstored as a 16-bit floating point data type. Additional operationsinclude performing a backward propagation operation associated with thelayer of the neural network to generate the scaled gradient tensor.

One embodiment provides for a graphics processing system comprising agraphics processor including a memory controller, a level-two (L2) cachememory coupled with the memory controller, and a multiprocessor coupledwith the memory controller, where the multiprocessor has a singleinstruction, multiple thread (SIMT) architecture including hardwaremultithreading. The multiprocessor can execute parallel threads ofinstructions associated with a command stream, where the multiprocessorincludes a set of functional units to execute at least one of theparallel threads of the instructions. The set of functional unitsinclude a mixed precision tensor processor and are configured to scaleloss data generated via tensor computations performed on by the mixedprecision tensor processor on a layer of a neural network, the loss datais stored as a floating-point data type, and the loss data is scaled bya scaling factor to enable a data distribution of a gradient tensorgenerated based on the loss data to be represented by a 16-bit floatingpoint data type. The graphics processing system additionally includes agraphics memory coupled with the memory controller of the graphicsprocessor. In a further embodiment, the graphics processing systemincludes a host interconnect bus coupled to the graphics processor andthe graphics memory to interconnect the graphics processor and thegraphics memory to a host system and/or host system processor. Thegraphics memory can include a graphics double data rate (GDDR) memory,which can include, for example a variant of GDDR5 or GDDR6 memory.

The embodiments described herein refer to specific configurations ofhardware, such as application specific integrated circuits (ASICs),configured to perform certain operations or having a predeterminedfunctionality. Such electronic devices typically include a set of one ormore processors coupled to one or more other components, such as one ormore storage devices (non-transitory machine-readable storage media),user input/output devices (e.g., a keyboard, a touchscreen, and/or adisplay), and network connections. The coupling of the set of processorsand other components is typically through one or more busses and bridges(also termed as bus controllers). The storage device and signalscarrying the network traffic respectively represent one or moremachine-readable storage media and machine-readable communication media.Thus, the storage devices of a given electronic device typically storecode and/or data for execution on the set of one or more processors ofthat electronic device.

Of course, one or more parts of an embodiment may be implemented usingdifferent combinations of software, firmware, and/or hardware.Throughout this detailed description, for the purposes of explanation,numerous specific details were set forth in order to provide a thoroughunderstanding of the present invention. It will be apparent, however, toone skilled in the art that the embodiments may be practiced withoutsome of these specific details. In certain instances, well-knownstructures and functions were not described in elaborate detail to avoidobscuring the inventive subject matter of the embodiments. Accordingly,the scope and spirit of the invention should be judged in terms of theclaims that follow.

What is claimed is:
 1. A graphics processor comprising: a memorycontroller; and a streaming multiprocessor coupled with the memorycontroller, the streaming multiprocessor to concurrently executemultiple thread groups, wherein the streaming multiprocessor includes asingle instruction, multiple thread (SIMT) architecture, the streamingmultiprocessor including: first circuitry to perform tensor operationsassociated with a first layer of a neural network; and second circuitryto: analyze statistics for output values of the tensor operations;determine a target format to convert the output values, the targetformat determined based on the statistics for the output values and aprecision associated with a second layer of the neural network; andconvert the output values to the target format.
 2. The graphicsprocessor as in claim 1, wherein the streaming multiprocessor isconfigured to determine the target format on a per-layer basis for theneural network.
 3. The graphics processor as in claim 2, wherein thetarget format is a floating-point format.
 4. The graphics processor asin claim 3, wherein the target format is selected from a plurality offloating-point formats.
 5. The graphics processor as in claim 4, whereinthe plurality of floating-point formats includes a first floating-pointformat having a first number of bits and a second floating-point formathaving a second number of bits.
 6. The graphics processor as in claim 5,wherein the first number of bits includes half the number of bits as thesecond number of bits.
 7. The graphics processor as in claim 6, whereinthe second circuitry is configured to scale the output values to fitwithin a representable range of the target format.
 8. The graphicsprocessor as in claim 7, wherein the statistics for the output valuesinclude a dynamic range of the output values.
 9. The graphics processoras in claim 8, wherein to scale the output values includes to adjust thedynamic range of the output values.
 10. The graphics processor as inclaim 1, further comprising a level-two (L2) cache coupled with thememory controller.
 11. The graphics processor as in claim 10, furthercomprising a high-bandwidth memory (HBM) device coupled with the memorycontroller, wherein the L2 cache is configured to cache data stored tothe HBM device.
 12. A method comprising: concurrently executing multiplethread groups via a streaming multiprocessor of a graphics processor,the streaming multiprocessor including a single instruction, multiplethread (SIMT) architecture; performing tensor operations via firstcircuitry of the streaming multiprocessor, the tensor operationsassociated with a first layer of a neural network; and via secondcircuitry of the streaming multiprocessor: analyzing statistics foroutput values of the tensor operations; determining a target format toconvert the output values, the target format determined based on thestatistics for the output values and a precision associated with asecond layer of the neural network; and converting the output values tothe target format.
 13. The method as in claim 12, further comprisingdetermining the target format on a per-layer basis for the neuralnetwork.
 14. The method as in claim 13, wherein the target format is afloating-point format.
 15. The method as in claim 14, wherein the targetformat is selected from a plurality of floating-point formats.
 16. Themethod as in claim 15, the plurality of floating-point formats includinga first floating-point format having a first number of bits and a secondfloating-point format having a second number of bits.
 17. The method asin claim 16, wherein the first number of bits includes half the numberof bits as the second number of bits.
 18. The method as in claim 17,further comprising scaling the output values to fit within arepresentable range of the target format.
 19. The method as in claim 18,wherein the statistics for the output values include a dynamic range ofthe output values and scaling the output values includes adjusting thedynamic range of the output values.
 20. A data processing systemcomprising: a memory device; and a graphics processor coupled with thememory device, the graphics processor comprising: a level-two (L2) cacheconfigured to cache data stored to the memory device; a memorycontroller coupled with the memory device and the L2 cache; and astreaming multiprocessor coupled with the memory controller, thestreaming multiprocessor to concurrently execute multiple thread groups,wherein the streaming multiprocessor includes a single instruction,multiple thread (SIMT) architecture, the streaming multiprocessorincluding: first circuitry to perform tensor operations associated witha first layer of a neural network; and second circuitry to: analyzestatistics for output values of the tensor operations; determine atarget format to convert the output values, the target format determinedbased on the statistics for the output values and a precision associatedwith a second layer of the neural network; and convert the output valuesto the target format.
 21. The data processing system as in claim 20,wherein the memory device is a high-bandwidth memory (HBM) device. 22.The data processing system as in claim 20, wherein the streamingmultiprocessor is configured to determine the target format on aper-layer basis for the neural network.
 23. The data processing systemas in claim 22, wherein the target format is a floating-point formatthat is selected from a plurality of floating-point formats.
 24. Thedata processing system as in claim 23, wherein the plurality offloating-point formats includes a first floating-point format having afirst number of bits, a second floating-point format having a secondnumber of bits, and the first number of bits includes half the number ofbits as the second number of bits.
 25. The data processing system as inclaim 24, wherein the second circuitry is configured to scale the outputvalues to fit within a representable range of the target format, thestatistics for the output values include a dynamic range of the outputvalues, and to scale the output values includes to adjust the dynamicrange of the output values.